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i understand that , but i have seen a suffix added to the netlist's ports
follow this procedure:
load the design in RTL compiler..
Then check out the hdl_libraries or libraries there(am not sure which one). go deep into the directory where u could observe the port of any gate.. there check out fot XOR3X4 , output Y in specific..
u will see lots of outputs with sufices..
i am sure they indicate something reg the drive strengths of the gates..