can TASK be used in synthesisable Verilog RTL code?

Status
Not open for further replies.

johnli100

Member level 1
Joined
Apr 13, 2004
Messages
32
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
243
rtl verilog task

can task be used in the synthesisable RTL code? If can, would someone please give me an example.
thanks!
 

verilog task rtl

No.

Never use that, although it is supported in IEEE P1364.1 / D1.6 .
Use function insteadly.
 

Yes, if your compiler supports it.

Here's an example copied from the Xilinx XST User Gude (a synthesis tool for FPGA).

Code:
module EXAMPLE (A, B, CIN, S, COUT);
  input [3:0] A, B;
  input CIN;
  output [3:0] S;
  output COUT;
  reg [3:0] S;
  reg COUT;
  reg [1:0] S0, S1, S2, S3;

  task ADD;
    input A, B, CIN;
    output [1:0] C;
    reg [1:0] C;
    reg S, COUT;

    begin
      S = A ^ B ^ CIN;
      COUT = (A&B) | (A&CIN) | (B&CIN);
      C = {COUT, S};
    end
  endtask

  always @(A or B or CIN)
    begin
    ADD (A[0], B[0], CIN, S0);
    ADD (A[1], B[1], S0[1], S1);
    ADD (A[2], B[2], S1[1], S2);
    ADD (A[3], B[3], S2[1], S3);
    S = {S3[0], S2[0], S1[0], S0[0]};
    COUT = S3[1];
  end
endmodule
Or do you need to see an example with a clock? I don't have one.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…