Can multiple interfaces be instansed together in system verilog?

[littlebu]

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Code Verilog - [expand]
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interface_instantiation ::=
interface_identifier [ parameter_value_assignment ] module_instance { , module_instance } ;

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above is interface instantiation syntax, seems multi interfaces (like an interface array) cannot be clarified together, is that ture?

what im looking for is:

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Code Verilog - [expand]
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axi_interface #(d_w(32)) [nr_of_ports-1:0] my_interface;

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is that possible?

Thanks

 

[dave_59]

You can certainly do that because if you dive into module_instance , it allows

name_of_instance ::=
      instance_identifier { unpacked_dimension }

The correct syntax will be

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Code Verilog - [expand]
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axi_interface #(d_w(32))  my_interface[nr_of_ports-1:0]();

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Note that you cannot use a variable to dynamically index into an instance array. The index must be a constant or generate loop variable. genver.

 

[littlebu]

Thanks! !

And more questions about interface:

1. Can such 2d interface array as a port?
2. How can I use modport in that case if Q1 is OK?

3. for example:

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Code Verilog - [expand]
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module axi_slave(
    my_axi_interface axi_master_interface[nr_of_axi_ports-1:0];
    clk,
    rstn
    );
    generate
    .*
    axi_mastere_interface[i].awready = '1;      // is that working?
    endgenerate
    endmodule
    
    module bench();
    my_axi_interface axi_master_interface[nr_of_axi_ports-1:0];
    axi_slave u_axi_slave(
    .axi_master_interface(axi_master_interface),            // Q: is this right?
    .*);
    endmodule

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Thanks