can "if" statement replace "for loop" in

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amitgangwar_vlsi

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hello everybody.......

can i replace "for loop" in VHDL using "if" or any other statement....

thanks in advance

amit gangwar
 

Re: can "if" statement replace "for loop&quot

I think CASE SELECT is better than if
:!:
 

Can you provide some example, as far as i know if you replace for with the if statement then the if statement will be a long list and it is inefficient to do that. Imagine that you replace the for i = 0, i <=100, i++; , how long the if statement you need to write........
 

Re: can "if" statement replace "for loop&quot

hello...
i can use case or if .but problem is that in place of next statement what can i use?????

i have to replace
for i in 1 to 3 loop
for j in 1 to 3 loop
statements;
next;
statements;
end loop;
end loop;

thanks in advance

amit gangwar
 

Re: can "if" statement replace "for loop&quot

if next statement means to skip some statements for certain conditions


it's infact and if / a conditional


and u neeed use another if here .
 

Re: can "if" statement replace "for loop&quot

u can refer the book which i m uploading
 

Re: can "if" statement replace "for loop&quot


hmm... you make me think a while

"for" statement is a loop statement and "if" statement is not.. "while" statement would be able to do the same as "for" statement
 

if statement gives a conditional check but we cant use for loops as easily as compared to if or if,else

so i will say that we can use but not with ease, we can do at the cast of complex programming
 

Re: can "if" statement replace "for loop&quot


If statement can replace the for statement but at the cost complexity.
For example,
for i=0, i < 3, i ++;
you can change to
i = 0;
if (i = 0) then
statement
statement
i++;
if (i = 1) then
statement(repeat)
statement(repeat)
i++
if (i = 2) then
statement(repeat)
statement(repeat)
i++
endif;
endif;
endif;

I think in programing nothing is impossible just that which way is more suitable and more efficient.
Anyway is just my 2 cents
 

hi
in vhdl the for loop statement is used for itreation
but the if statement is used for conditional check
i think if statement is not replace by for loop satatement

Added after 3 minutes:

in if statement the specified condition is check but in the for loop statement the loop is start until the given limit is end.
 

Re: can "if" statement replace "for loop&quot

hi


if is used for conditional statements, and for is used for looping or iteration ...............replacing if with for statements is possible but will make ur code long and complex.
 

Re: can "if" statement replace "for loop&quot

laststep wrote:
If statement can replace the for statement but at the cost complexity.
For example,
for i=0, i < 3, i ++;
you can change to
i = 0;
if (i = 0) then
statement
statement
i++;
if (i = 1) then
statement(repeat)
statement(repeat)
i++
if (i = 2) then
statement(repeat)
statement(repeat)
i++
endif;
endif;
endif;

I think in programing nothing is impossible just that which way is more suitable and more efficient.



it is possible if there is only one loop in my program.
but if there is one loop and within that loop there are two three more loop then how it can be possible.....
 

I think multi loop in if statement is still possible. for example if we have 2 for loop (i and j), just treat it as a combine number.
So, your statement will end up like this
If (i == 0 and j ==0)
statement;
j ++;
if (i == 0 and j ==1)
statement(repeat);
...
...
...
...

endif;

But is going be a very long list.
 

i think it will be ok
but , sometimes it 'll be too complex !
 

Re: can "if" statement replace "for loop&quot

i also agree it will become very complex n u can perform concatenation of i and j and then perform if conditions...

a<= i&j;

if(a="00")
..
..
...


endif;
 

Re: can "if" statement replace "for loop&quot


a for takes 2 ins cycles a next 1

this is the rule

so instructions = (((3 * runtimes) * time) + (instruction used in a single event * runtimes))
 

Re: can "if" statement replace "for loop&quot

@VSMVDD: what statement are you quoting here?
I think, in C programming, that you are referring to, it's impossible to say exactly that a certain construct would be more effective in terms of instructions cycles than another. If it's functional equivalent, the compiler may optimize it to the same code.

If you wan't to optimize speed without considering code readability, than you could use assembler. High language programming style should basically achieve clear representation of constituent algorithms and data structures (that's not my idea, it's Dyjkstra, but it should be reminded sometimes).

In VHDL programming, which has been the original thread topic, the situation is even simpler. Cause the code doesn't create a sequential execution flow rather than parallel logic, all functional equivalent "programs" usually end up in the same logic. Thus programming style is even more a matter of readability and clear expression of algorithms.

Regarding amit gangwars original question, I miss the reason, why to replace the VHDL for loop, but probably the problem has been solved in the meantime.

Regards,
Frank
 

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