u24c02
Advanced Member level 1
Hi all
I have gatenetlist for postsim and SDF. This files are produced from post simulation.
Of course, scan and Clock tree synthesis was did.
I'm going to apply this postsim gatenetlist to xilinx ISE with SDF for make FPGA bit file.
That is, i want to apply FPGA to netlist included delay information.
But i cant now know about the manners.
So i want to know how can i use gate netlist with SDF(from dc synthesis).
I have gatenetlist for postsim and SDF. This files are produced from post simulation.
Of course, scan and Clock tree synthesis was did.
I'm going to apply this postsim gatenetlist to xilinx ISE with SDF for make FPGA bit file.
That is, i want to apply FPGA to netlist included delay information.
But i cant now know about the manners.
So i want to know how can i use gate netlist with SDF(from dc synthesis).