instantiate verilog ip in vhdl
sometimes the top module of individual VHDL blocks are written using verilog, because i believe its simpler to instantiate it in verilog than in vhdl, where component instantiation along with port map has to be done separately.
Also, i'm not so sure about hierarchical access to internal registers(which verilog supports) will be possible in VHDL. i'd love to proven wrong on this one.
Btw, for the example posted above, if i try to compile using modelsim (vlog) , i get a compile error because libraries are not part of verilog. How to overcome this situation?