Hi, rca,
I used the "set_dont_use" to exclude most cells except the "and2, or2, inverter and FD1". Because in my project, other cells are not permited. I mean, I must constraint the types of gates, but this constraints are not possible in FPGA synthesizer. So I should first do it in ASIC synthesizer to get the gate-level descripted .v file (which is comprised of the above mentioned 4 types of cells) than then transfer it to FPGA for the following work.
That's why I do it in ASIC tool and then jump to FPGA tools.
The problem now is the one I asked in the thread. In xilinx FPGA, ff has no negative ouput. So I must disable the usage of the negative output of FD1 in DC synthesis in order to match the hardwares in FPGAs.