Can I add more BUFG manually for high fan-out\loads for clk

[xtcx]

Hi dear friends, I'm using a 2000k Xc3S and hence my design too is quite complex. Clk used is single input of 100Mhz from gclk1 and is the only clock in project. Not used DCM so far. Now in PAR the clock statistics shows a high clk load over 8000. This means a heavy fan-out. So could you tell me if this is gonna affect my design?.I'm getting a poor clock period of 62MHz only but I need 100MHz operation speed!......does using global clock resources such as BUFGP help reduce the loads(fan-out) and increase performance or clk timming?..Or will the tool do it for me?..The tool is inferring not more than i BUFG but still fan-out is high!....All I see is that it says 1 BUFG is inferred for clk. But the report says clk load is 8235.I'm using Xilinx ISE 8.2i.
Could some one clarify this?...It'd be a great help

 

[shitansh]

Re: Can I add more BUFG manually for high fan-out\loads for

By proper setting of constraint for output load capacitance, I think tool will do it for you.

 

[xtcx]

Re: Can I add more BUFG manually for high fan-out\loads for

so dont I have to worry about this even if it exceeds more loads?.....

 

[shitansh]

Re: Can I add more BUFG manually for high fan-out\loads for

If you give large constraint for output load capacitance tool will not grant, untill tool accepts constraint you need not to worry.

 

[TA37]

I believe that global clock resources are actually buffered in a tree throughout the chip, which is why you have a limited number and non-global clock routing is suboptimal.

Look at your tools to see where the 62 MHz critical path is and how much is clk skew vs logic delay. If it is a long Q-to-D logic path then no clk tricks will help you; you have to pipeline better.