xtcx
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Hi dear friends, I'm using a 2000k Xc3S and hence my design too is quite complex. Clk used is single input of 100Mhz from gclk1 and is the only clock in project. Not used DCM so far. Now in PAR the clock statistics shows a high clk load over 8000. This means a heavy fan-out. So could you tell me if this is gonna affect my design?.I'm getting a poor clock period of 62MHz only but I need 100MHz operation speed!......does using global clock resources such as BUFGP help reduce the loads(fan-out) and increase performance or clk timming?..Or will the tool do it for me?..The tool is inferring not more than i BUFG but still fan-out is high!....All I see is that it says 1 BUFG is inferred for clk. But the report says clk load is 8235.I'm using Xilinx ISE 8.2i.
Could some one clarify this?...It'd be a great help
Could some one clarify this?...It'd be a great help