I am just wondering, do we need to run the code coverage at the gate-level netlist?
Can the code coverage from cadence support code coverage at the gate-level netlist? Thanks
i think no need for that, as you do it in RTL to ensure and verify your code. after you synthesize it, be sure it is accurate as it is automatic synthesis.
I am just wondering, do we need to run the code coverage at the gate-level netlist?
Can the code coverage from cadence support code coverage at the gate-level netlist? Thanks
Wow, the FSM-coverage tool can recognize state-machines in a netlist-representation? Or does the user need to declare the state-machine ahead of time, so the tool is aware of it?
I am just wondering, do we need to run the code coverage at the gate-level netlist?
Can the code coverage from cadence support code coverage at the gate-level netlist? Thanks
coverage in gate level may be not as coverage in the RTL, as we all know coverage in
RTL is a measure for the executed functions and test plans. but in gate level we may take its meaning as ensuring that the synthesized design is as same as the rtl. i.e if your design has blocks A,B and C in RTL, we may need to cover that these blocks are truly synthesized and our function is still accurate (it is most likely gate level simulation).
about a tool that makes that--> i know Formal Pro from mentor graphics do that you can find more details about it if you visited www.mentor.com/products you can find it under the topice "scalable verification"