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due to signal electro migration the metal ions movement occurs which cause voids or hillocks and ultimately results in shorts or open. so they degrade the signal and design performance.
How is it different from power electromigration that occurs in power lines (vdd and vss). Is signal electromigration in an issue in digital asic design or analog electric design.
Basically for the current to flow thro the various metal lines there should be minimum amount of metal width. The DRC document for the particular PDK /Technology highlights the min. width of the metal for a certain current.
For ex. for 1mA of Current, the width of the metal should be 1um at say 125 deg C.
So based on the temp and also the process this standards vary.
Electromigration is the movement of metal ions in a conductor, which depends upon the current density , if ur current density say 2mA is flowing in a metal layer of 1micron then u will get electromigration problems which causes metal layer to break , That is if the current flow is unidirectional then you will get electromigration. And it happens only in the case of Power lines not signal lines,
The problem which occurs in Signal nets is called as Self Heating and it is because the signal flows bidirectionally.
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