I want to design a comparator used in a SAR ADC.
The SAR ADC is 8bits 50k/s ,under 3.3v power supply, 0.18um process.
Can anyone recommend a comparator circuit ?
Thanks a lot.
1.which topology should i choose?
2.use latch-type comparator or opamp-type comparator?
3.should the offset-cancellation be considered?
4.should I design a clock-generate circuit for control logic?
5.any design suggestions to share?
For speed you can use a preamp followed by regenerative latch architecture. Since it is only 8bits the preamp may not reqiure autozeroing. The preamp gain will depend on the worst case offset of the regenerative latch. If latch has 20mV offset then to make the inpur reffered offset less than 0.5lsb at 8bits a gain of 20mV/ (0.5*lsb) is needed. Try designing preamplifier with resistive load to increase speed.
Refer Allen Holberg for Comparator design