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Can anyone recommend a comparator circuit used for SAR ADC?

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Full Member level 6
Aug 2, 2005
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I want to design a comparator used in a SAR ADC.
The SAR ADC is 8bits 50k/s ,under 3.3v power supply, 0.18um process.
Can anyone recommend a comparator circuit ?
Thanks a lot.

1.which topology should i choose?
2.use latch-type comparator or opamp-type comparator?
3.should the offset-cancellation be considered?
4.should I design a clock-generate circuit for control logic?
5.any design suggestions to share?

Re: Can anyone recommend a comparator circuit used for SAR A

I've design an 8-bit comparator also for SAR

I've used op-amp type of comparator....two stage comparator..simple design than others.

I'm able to get the resolution down to only need 12.8mV for 8 bit.

Well my SAR is slower than comparator need at least 50ns to transfer signal...

Lower tail current will give u more sensitive two stage comparator.

Added after 1 minutes:

Yes offset canclelation is high performance device

I think the comparator need no clock if before that it got sample and hold

Re: Can anyone recommend a comparator circuit used for SAR A

Thanks for your reply.
Did you design the two-stage comparator circuit just like the circuit in allen's book?

If you have refered some papers, could you recommend to me?

For speed you can use a preamp followed by regenerative latch architecture. Since it is only 8bits the preamp may not reqiure autozeroing. The preamp gain will depend on the worst case offset of the regenerative latch. If latch has 20mV offset then to make the inpur reffered offset less than 0.5lsb at 8bits a gain of 20mV/ (0.5*lsb) is needed. Try designing preamplifier with resistive load to increase speed.
Refer Allen Holberg for Comparator design

hope this helps

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