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why the bottom-rightmost ff's clk line connected to ground ? i tried the simulation in cadence & i'm not getting it right ..can anybody help me to figure out the problem
Well, that looks a little peculiar to me. Assuming that bottom right FF's SET signal is CLK (that's a terrible way to draw it, BTW), then the Q for that FF will go high on the first rising CLK edge. That, in turn, will clock the COMP signal to D0.
But that can't be right. That means the upper right FF has no output connected. Maybe the SET of the bottom left FF is supposed to go to Q of the uppper. Or Qnot. Maybe you need a better schematic.
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