Queues and stacks (FIFO and LIFO) are commonly used structures and are well described in many textbooks. I think you should be able to do this from scratch. Feel free to post with SPECIFIC questions about the implementation, but I think you should take a shot at it first (at least try to put something together, then ask the forum for help).
always @(posedge clk)
if (rst)
begin
// fcounter <= 0;
// rd_ptr <= 0;
wr_ptr <= 0;
end
else if (clr)
begin
// fcounter <= 0;
// rd_ptr <= 0;
wr_ptr <= 0;
end
else
begin
if (write && (~full))
begin
wr_ptr <= wr_ptr+1;
// fcounter <= fcounter+1;
end
else
begin
wr_ptr <= wr_ptr;
// fcounter <= fcounter;
end
end
//Read process
always @(posedge clk)
if (rst)
begin
// fcounter <= 0;
rd_ptr <= 0;
// wr_ptr <= 0;
end
else if (clr)
begin
// fcounter <= 0;
rd_ptr <= 0;
// wr_ptr <= 0;
end
else
begin
if (read && (~empty))
begin
rd_ptr <= rd_ptr+1;
// fcounter <= fcounter-1;
end
else
begin
rd_ptr <= rd_ptr;
// fcounter <= fcounter;
end
end
always @(posedge clk)
if (rst)
begin
fcounter <= 0;
end
else if (clr)
begin
fcounter <= 0;
end
else
begin
if ((write && (~full))&&~(read && (~empty)))
begin
fcounter <= fcounter+1;
end
else if ((write && (~full))&&(read && (~empty)))
begin
fcounter <= fcounter;
end
else if (~(write && (~full))&&(read && (~empty)))
begin
fcounter <= fcounter-1;
end
else if (fcounter == `DEPTH+1)
begin
fcounter <= 0;
end
end
// Process for Status Signals
always @(posedge clk)
if (rst)
begin
empty <= 1'b1;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
else if (clr)
begin
empty <= 1'b1;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
else
begin
case (fcounter)
`DEPTH: begin
empty <= 1'b0;
full <= 1'b1;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
`DEPTH -1: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b1;
slast <= 1'b0;
first <= 1'b0;
end
`DEPTH -2: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b1;
first <= 1'b0;
end
1: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b1;
end
0: begin
empty <= 1'b1;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
default: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
Thank u ... this code helped me to understand n to draw
---------- Post added at 07:40 ---------- Previous post was at 07:36 ----------
its not that i dint tried .... i have tried it and drawn diagram also but i want to know when the fifo controller sends Fifo empty and fifo half full signal to FIFo back
Thank u ... this code helped me to understand n to draw
---------- Post added at 07:40 ---------- Previous post was at 07:36 ----------
its not that i dint tried .... i have tried it and drawn diagram also but i want to know when the fifo controller sends Fifo empty and fifo half full signal to FIFo back
For future reference, I would recommend attaching a copy/image of what you have done so far, then asked specifically where the FIFO Empty and FIFO Half-Full signals would originate. Asking specific questions will get you specific answers (and some general ones, too). That way it doesn't look like you are trying to get the folks on this forum to do your work for you.
Its OK... I understand that it could be tough sometimes understanding the most basic concepts, or getting resources/help when you are at very beginner level.
"The following is a small design of a FIFO, which is built of Flip-Flop devices. I found the design some where on the web, fixed some bugs, created a test bench to test it and PERL script to automate the testing..."
**broken link removed**