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can anybody help me to draw a state machine for fifo

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tulsi

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Hi,
pls help me to draw a state machine for fifo with all states and their description . pls help me its urgent

Thanks
 

enjunear

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This sounds suspiciously like a homework problem.

Queues and stacks (FIFO and LIFO) are commonly used structures and are well described in many textbooks. I think you should be able to do this from scratch. Feel free to post with SPECIFIC questions about the implementation, but I think you should take a shot at it first (at least try to put something together, then ask the forum for help).
 

siddharthakala

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What kind of FIFO do you need synchronous or asynchronous.

Synchronous is sort of simple while asynchronous is a bit complex. Asynch involves clock domain crossing, gray codes and stuff.

Following is the link for asynchronous FIFO:

Asynchronous FIFO

I couldnt attach the synchronous fifo files for some reason, so I am just copying the code here. (It is not an optimized code)

FIFO TOP MODULE----------


`define WIDTH 32
`define DEPTH 4
`define FCWIDTH 2


module FIFO_topmodule
( input Clk,
input Rst,
input [`WIDTH-1:0] DIn,
input Write,
input Read,
input Clr,
output Empty,
output Full,
output [`WIDTH-1:0] DOut,
output Last,
output SLast,
output First
);

wire [`FCWIDTH-1:0] rd_wire,wr_wire;

FIFO_controller fifo1(
.clk(Clk),
.rst(Rst),
.write(Write),
.read(Read),
.clr(Clr),

.empty(Empty),
.full(Full),
.last(Last),
.slast(SLast),
.first(First),
.rd_ptr(rd_wire),
.wr_ptr(wr_wire)
);

FIFO_memblk fifo2(
.clk(Clk),
.write(Write),
.read(Read),
.rd_addr(rd_wire),
.wr_addr(wr_wire),
.datain(DIn),
.dataout(DOut)
);



endmodule


-----------------------

FIFO CONTROLLER -----------


`define WIDTH 32
`define DEPTH 4
`define FCWIDTH 2

module FIFO_controller(
input clk,
input rst,
input write,
input read,
input clr,

output reg empty,
output reg full,
output reg last,
output reg slast,
output reg first,
output reg [`FCWIDTH-1:0] rd_ptr,
output reg [`FCWIDTH-1:0] wr_ptr
);

//Write process
reg [`FCWIDTH:0] fcounter;

always @(posedge clk)
if (rst)
begin
// fcounter <= 0;
// rd_ptr <= 0;
wr_ptr <= 0;
end
else if (clr)
begin
// fcounter <= 0;
// rd_ptr <= 0;
wr_ptr <= 0;
end
else
begin
if (write && (~full))
begin
wr_ptr <= wr_ptr+1;
// fcounter <= fcounter+1;
end
else
begin
wr_ptr <= wr_ptr;
// fcounter <= fcounter;
end
end

//Read process
always @(posedge clk)
if (rst)
begin
// fcounter <= 0;
rd_ptr <= 0;
// wr_ptr <= 0;
end
else if (clr)
begin
// fcounter <= 0;
rd_ptr <= 0;
// wr_ptr <= 0;
end
else
begin
if (read && (~empty))
begin
rd_ptr <= rd_ptr+1;
// fcounter <= fcounter-1;
end
else
begin
rd_ptr <= rd_ptr;
// fcounter <= fcounter;
end
end


always @(posedge clk)
if (rst)
begin
fcounter <= 0;
end
else if (clr)
begin
fcounter <= 0;
end
else
begin
if ((write && (~full))&&~(read && (~empty)))
begin
fcounter <= fcounter+1;
end
else if ((write && (~full))&&(read && (~empty)))
begin
fcounter <= fcounter;
end
else if (~(write && (~full))&&(read && (~empty)))
begin
fcounter <= fcounter-1;
end

else if (fcounter == `DEPTH+1)
begin
fcounter <= 0;
end
end

// Process for Status Signals
always @(posedge clk)
if (rst)
begin
empty <= 1'b1;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
else if (clr)
begin
empty <= 1'b1;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
else
begin
case (fcounter)
`DEPTH: begin
empty <= 1'b0;
full <= 1'b1;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
`DEPTH -1: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b1;
slast <= 1'b0;
first <= 1'b0;
end
`DEPTH -2: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b1;
first <= 1'b0;
end
1: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b1;
end
0: begin
empty <= 1'b1;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end
default: begin
empty <= 1'b0;
full <= 1'b0;
last <= 1'b0;
slast <= 1'b0;
first <= 1'b0;
end


endcase

end

endmodule

---------------------------
FIFO MEMORY BLOCK--------------------

`define WIDTH 32
`define DEPTH 4
`define FCWIDTH 2

module FIFO_memblk(
input clk,
// input rst,
// input clr,
input write,
input read,
input [`FCWIDTH-1:0] rd_addr,
input [`FCWIDTH-1:0] wr_addr,
input [`WIDTH-1:0] datain,
output reg [`WIDTH-1:0] dataout
);

reg [`WIDTH-1:0] MEMORY[0:`DEPTH-1];

always @(posedge clk)

begin
if (write)
MEMORY[wr_addr] <= datain;
else
MEMORY[wr_addr]<= MEMORY[wr_addr];
end


always @(posedge clk)

begin
if (read)
dataout <= MEMORY[rd_addr];
else
dataout <= 0;
end

endmodule
 
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    tulsi

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tulsi

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Thank u ... this code helped me to understand n to draw

---------- Post added at 07:40 ---------- Previous post was at 07:36 ----------

its not that i dint tried .... i have tried it and drawn diagram also but i want to know when the fifo controller sends Fifo empty and fifo half full signal to FIFo back
 

enjunear

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Thank u ... this code helped me to understand n to draw

---------- Post added at 07:40 ---------- Previous post was at 07:36 ----------

its not that i dint tried .... i have tried it and drawn diagram also but i want to know when the fifo controller sends Fifo empty and fifo half full signal to FIFo back

For future reference, I would recommend attaching a copy/image of what you have done so far, then asked specifically where the FIFO Empty and FIFO Half-Full signals would originate. Asking specific questions will get you specific answers (and some general ones, too). That way it doesn't look like you are trying to get the folks on this forum to do your work for you.
 

siddharthakala

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Its OK... I understand that it could be tough sometimes understanding the most basic concepts, or getting resources/help when you are at very beginner level.
 

pini_1

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Maybe this post can help you.

"The following is a small design of a FIFO, which is built of Flip-Flop devices. I found the design some where on the web, fixed some bugs, created a test bench to test it and PERL script to automate the testing..."
VHDL, verilog, design, verification, scripts, ...
 

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