Mr.Cool
Advanced Member level 2
sorry for my basic question, but i am not entirely sure of capability of a CPLD.
let's say i have two incoming signals and i want to know how much time passes between the two. so, when signal_1 goes high, it could trigger an 8-bit synchronous counter and the counter would stop when signal_2 goes high thus the measurement how how much time is between the two signals has been determined and "stored" in memory as a value with variable name delay_12. sound reasonable?
then, this is my question. i want for all future events when signal_1 goes high, to add delay_12 to it. so that output_1 = signal_1 + delay_12.
is this possible?
how would this normally be accomplished? simulate in simulink first and then simulate in VHDL and compare the two?
let's say i have two incoming signals and i want to know how much time passes between the two. so, when signal_1 goes high, it could trigger an 8-bit synchronous counter and the counter would stop when signal_2 goes high thus the measurement how how much time is between the two signals has been determined and "stored" in memory as a value with variable name delay_12. sound reasonable?
then, this is my question. i want for all future events when signal_1 goes high, to add delay_12 to it. so that output_1 = signal_1 + delay_12.
is this possible?
how would this normally be accomplished? simulate in simulink first and then simulate in VHDL and compare the two?