Can a typical CPLD do this?

[Mr.Cool]

sorry for my basic question, but i am not entirely sure of capability of a CPLD.

let's say i have two incoming signals and i want to know how much time passes between the two. so, when signal_1 goes high, it could trigger an 8-bit synchronous counter and the counter would stop when signal_2 goes high thus the measurement how how much time is between the two signals has been determined and "stored" in memory as a value with variable name delay_12. sound reasonable?

then, this is my question. i want for all future events when signal_1 goes high, to add delay_12 to it. so that output_1 = signal_1 + delay_12.

is this possible?

how would this normally be accomplished? simulate in simulink first and then simulate in VHDL and compare the two?

 

[TrickyDicky]

Its a little vague - what exactly do you mean by

output_1 = signal_1 + delay_12?

is output 1 just a delayed version of the input? what is the wider application?

but it sounds pretty straight forward. I doubd many people use simulink. Most would probably just code it up, write a testbench and put it on the chip.

 

[Mr.Cool]

yes that's right, output_1 is just the delayed version of signal_1. i guess i have to go read some digital design books or something to learn how to do this.

so the first part, determining the delay. does a synchronous counter sound like a good way to do that? then i want to preserve this result for later use, does that mean i store this value in CPLD RAM?

 

[TrickyDicky]

synchronous counter yes. Storage of the value would be in another register.
The input will go into a shift register, and the stored counter value will then just select which tap from the shift reg to use.