Hi,
thank you for your reply.
I guess I was a bit too fast.
My SPI implementation itself seems to be fine, however I am messing up the timing it seems, and I'm able to break it at very simple conditions it seems.
Seems like I hit a perfect example how to do something wrong for learning... I'll post an update as soon as I figure out what's wrong.
seems like the gated input clock (SPI clock) from the master is not the issue and that's just what I wanted to be sure about.