Calibre PEX

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ahmedatef0

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I runned PEX on my LNA design & it showed no errors or warnings but when I tried to simulate it it gave me the following error.
 

Your setup is broken. It is however hard to say exaclty where. It could be the cdlin process when calibre generates the schematics.

In the calibre view - do you see the capacitance?

Could it be that you should use some other run deck for _rf components?

If you check the netlist generated by LVS; how is the component listed there?
 

It looks like you are simulating a schematic netlist, not the post-layout netlist.
Then why are you asking about PEX?
 

(It says calibre in the cell view, and transistor numbering is mentorgraphicsy.)

I believe the CDF parameters have not been set correct during cdlin/calibre view.

Does the calview.cellmap file contain info on the capacitors?
Does the auCdl CDF parameter have information on the capacitors?

Neverheless, it sounds like you would need to check the PDK setup
 

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