Hi NOmalum
first of all make sure that this is not an actual error that escaped the previous version of the rules, if the layout pcell is actually a match for the schematic symbol then verify which netlist (layout or source) is not correct.
If it is the source, then change the CDF of the auCdl simulator, which is used by Calibre for LVS netlisting
If it is the layout netlist that uses the wrong subtype then you need to change the rules and modify the extraction rule accordingly
Let us know if you need more help