Amrsfmt
Junior Member level 1
tspc rabaey
Hi All,
I'm currently working on something related with my masters. I'm facing a problem finding literature related with calculating maximum and minimum frequency of operation of the D-FF.
I understand that improper sizing of transistors may lead to improper operation. Please refer to P.353 in Rabaey's book "Digital Integrated Circuits", Example 7.4.
I understand also that leakage current affect the operation of TSPC D-FF because it changes the voltage on the internal nodes where the values are stored. Low frequency operation of TSPC cell then may be significantly affected.
What I'm looking for is What is the mathematical relation between transistors sizes and the minimum frequency of operation and maximum frequency of operation.
Thanks,
Amrsfmt
Hi All,
I'm currently working on something related with my masters. I'm facing a problem finding literature related with calculating maximum and minimum frequency of operation of the D-FF.
I understand that improper sizing of transistors may lead to improper operation. Please refer to P.353 in Rabaey's book "Digital Integrated Circuits", Example 7.4.
I understand also that leakage current affect the operation of TSPC D-FF because it changes the voltage on the internal nodes where the values are stored. Low frequency operation of TSPC cell then may be significantly affected.
What I'm looking for is What is the mathematical relation between transistors sizes and the minimum frequency of operation and maximum frequency of operation.
Thanks,
Amrsfmt