Calculating Avg Circuit Fan-in

[abhishektyagi]

Hi Everyone,
I have access to the RTL of an IP and can generate a netlist too by doing the synthesis.

I am interested in calculating the average fan-in to a flop in the design. Is there a tool in the ASIC pipeline that can do that?

Any input would be appreciated.

 

[Qwerty112233]

How do you define fan in, immediate connections coming into a flop input pin? Or sequential start points driving a flop d pin?

I'm thinking if there's over counting in getting
All flops, then their D pin nets, then getting drivers of those nets.

Either ways, you could uniquely count this list or as is..then as a last step divide by total flops to get the average?

 

[Qwerty112233]

How do you define fan in, immediate connections coming into a flop input pin? Or sequential start points driving a flop d pin?

I'm thinking if there's over counting in getting
All flops, then their D pin nets, then getting drivers of those nets.

Either ways, you could uniquely count this list or as is..then as a last step divide by total flops to get the average?

Perhaps it's better to use all fanin with -level or startpoints switch.

 

[ThisIsNotSam]

load the netlist into innovus, use the dbget interface to traverse the list of flip-flops and get their fanins/fanouts

something similar should be possible in Genus as well