calculate transistor width value for clock buffer in standard cell library.

[siddun2]

Hi,

Anybody could explain the method to determine transistor(width) values for clock buffer in standard cell library?

TIA,
Siddu

 

[Somashekhar]

In Clock buffers rise & fall time are balanced. So while designing clock buffer Beta ratio should be chosen such that clock buffer/inverter rise & fall time should be same.

 

[siddun2]

Yes Somashekhar,

I am considering both tran ratio & delay ratio equals to one. Since there are 4 transistors in clock buffer, what's the optimum way of modeling them in spice.

-SIddu Nugli