latebloomer
Newbie level 5
Determine the minimal clock period TW for the following circuit. Use the following delay values for the flip-flops and gates.
Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns
Inverter: 2 ≤ tPINV ≤ 12
XOR Gate: 7 ≤ tXOR ≤ 22
1.Work the problem under the assumption that the clock is
symmetrical. That is, it is high for 50% of the clock period and low for
50% of the clock period.
2.Work the problem under the assumption that the clock is high
for 20% of the clock period and low for 80% of the clock period.
Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns
Inverter: 2 ≤ tPINV ≤ 12
XOR Gate: 7 ≤ tXOR ≤ 22
1.Work the problem under the assumption that the clock is
symmetrical. That is, it is high for 50% of the clock period and low for
50% of the clock period.
2.Work the problem under the assumption that the clock is high
for 20% of the clock period and low for 80% of the clock period.