calculate min clock period under different assumptions

[latebloomer]

Determine the minimal clock period TW for the following circuit. Use the following delay values for the flip-flops and gates.
Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns
Inverter: 2 ≤ tPINV ≤ 12
XOR Gate: 7 ≤ tXOR ≤ 22

1.Work the problem under the assumption that the clock is
symmetrical. That is, it is high for 50% of the clock period and low for
50% of the clock period.

2.Work the problem under the assumption that the clock is high
for 20% of the clock period and low for 80% of the clock period.

 

[latebloomer]

so what will b e the difference between 1)and 2)

 

[Syswip]

Hi latebloomer,

I didn't calculate the exact timings but as I can see from your picture your critical timing path is from Q1/Q3 to the input of 1st flipflop.
1st flipflop is positive edge and Q1/Q3 is negative edge. It means the that critical timing path is starting from negedge and ending to posedge. In this case if you increase clock low time (80%) you max frequency will be increased.

Bests,
Syswip
http://syswip.com/

 

[latebloomer]

I don't know what is the relationship between %high clock with the minimum period.

Disregard the 2 assumptions,i get.

tPINV + tPFF + tXOR =< TW - tsu
12 + 14 +22 =< TW -6
TW >= 54

so what will change if we take the assumptions into account?

 

[Syswip]

Is it possible to have tPFF less then hold time?

 

[latebloomer]

it's possible.Can you explain how is the clock period reduced if you increase low time to 80% by calualting the exact things?

 

[Syswip]

As I understand tPFF is a FF input to output delay after clock edge.
Data hold time is a data stable time on the FF output after clock edge.
I didn't understand yet how it's possible to have hold time more than tPFF.

Now lets consider your equation.
It is partially correct.

tPINV + tPFF + tXOR =< TW - tsu

TW is clock period from posedge to posedge. But in this case your timing path should be calculated from negedge to posedge like this:

tPINV + tPFF + tXOR =< TW - tsu - T(high)
TW - T(high) >= 54
TW >= 54 + T(high)
If you decrease T(high) time your frequency will go up.

I hope this will help you.

Syswip,
http://syswip.com/

 

[latebloomer]

TW >= 54 + T(high)

so when T(high)=0,we can have the maximum frequency.but is that possible? which means we don't have any high clock during each TW

 

[Syswip]

Of course no.
You also has constraint for clock high duration.

t(high) = tPFF + tsu - tPINV = 14 + 6 -12 = 8.

So you have t(low) 54 and t(high) 8.

now if you have a clock 50% the full period is 54 + 54

54 + 8 = 62 this is the best ratio. 95% and 5%

 

[latebloomer]

t(high) = tPFF + tsu - tPINV = 14 + 6 -12 = 8.

I think you should use tpinv=2 in this case considering the path Q2-D3

 

[Syswip]

If you use 2 then t(high) = 18

Your min clock during 80%, 20% will be

TW = 90

It still less than if you have a clock 50% 54 + 54 = 108

I hope now it's clear for you why your max clock freq is higher when you have 80%, 20% cycle.

Best Regards,
Tiksan,
http://syswip.com/

 

[jayTudu]

Hi, thanks for posting nice puzzles.

Here is my attempt.
1) TW = (12 + 22) * 2 = 68 based on 50% criteria
I have not added set up time, bcoz inverter delay is > set up time
2) 12 + 22 = 34ns clock should remain in negative level. and 14 ns it should be in positive level.
putting 20% and 80% criteria will make the period TW = 70ns
Correct me if I am wrong.

 

[Syswip]

Hi jayTudu,

If you look at the timing diagrams you will see that clock should stay in low level
54 ns.

tPFF + tsu + tPINV + tXOR

 

[latebloomer]

t(high) = tPFF + tsu - tPINV
where does this come from

what i mean is youshould use Min tp INV instead of Max tp Inv to ensure your lowest thigh

 

[Syswip]

t(high) = tPFF + tsu - tPINV
where does this come from

Your first FF starting to pass input data to the output after posedge clk. The data should be available at Q1 tsu time before negedge clock.
Without INV delay t(high min) = tPFF + tsu. I hope this is clear for you.
INV delays clock edge to the second FF. It means we have more time so we can reduce
t(high min) time.
That's why we have t(high) = tPFF + tsu - tPINV equation.

Don't ask me why it is negative when tPINV is too big



I hope I helped you.

Best Regards,
Tiksan,
http://syswip.com/

 

[latebloomer]

But in this case your timing path should be calculated from negedge to posedge like this:

tPINV + tPFF + tXOR =< TW - tsu - T(high)
TW - T(high) >= 54
TW >= 54 + T(high)
why we need to count from negedge to psedge if we have the assumpations? Without assumpation and if without assumptions, it's just 54 for min Tw?