Cadence - when two individual components are connected , the circuit is not working

[pashwin92]

I did my full adder circuit and created a symbol . Also i did an AND gate and created the symbol.
Both the circuits are working correctly when checked separately and i got 1.8v for logic 1 and 24e-9 for logic 0.

I created a new schematic with the output of AND gate going to the Apin of the full adder .
Now when i simulate , the output of my AND gate is not Zero or One . It comes to be 322e-3.

Please let me know what am i doing wrong .

Thanks in advance .

 

[erikl]

... the output of my AND gate is not Zero or One . It comes to be 322e-3.

322mV is a (logical) Zero.

 

[pashwin92]

Sorry for late reply .

But when its 322mV , the output of the adder is not correct . It takes it to be logic one .

 

[drabos]

I assume you use standard CMOS logic. Try to increase the driver strength of your AND gate.

 

[pashwin92]

I corrected it .

I used transmission gate for XOR in the adder circuit and it created the problem . When i replaced it by Standard CMOS , it started working

Anyways , thanks very much