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[SOLVED] Cadence Virtuoso - Design Rule Check clearing erros

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lifeislife

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Hello,


I am completely new to this, I am trying to complete a module on Cadence Virtuoso Education kit. However, I got stuck on clearing some errors related to Design Rule Check (DRC). The circuit built is attached and layout. Anyone can help on this are these errors or just warnings I can ignore and proceed, please advice.

Thank you.


Layout.png
Schematic.png


PVS_DRC Result Viewer.png
PVS_Reports DRC.png


PVS_Reports DRC_1.png
PVS_Reports DRC_2.png
 

You have created a latchup by violating the rule about maximum distance between contacts to well or substrate.
On your layout i can see two guard rings, one connected to gnd around nfets (if it is made on psub then is good) and one large connected to vdd - if this one is the only one for nwell then you have issue here. Remove this outer ring, enclose every pfet with such nwell ring.
 
Thank you for your reply. nWell around pfet was missing solved it errors cleared
--- Updated ---

However there is another error in LVS. Unmatched schematic pin labels. I tried tracing it back, but in vain. Any chance you can help on this ?

Thank you.
 

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  • Layout1.png
    Layout1.png
    44.5 KB · Views: 199
  • LVS Error.png
    LVS Error.png
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  • Layout1_vin.png
    Layout1_vin.png
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  • Layout1_vout.png
    Layout1_vout.png
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Last edited:

You are using labels as pins. Vin and Vout labels are attached to nothing. The center of label (visible cross) should be placed on metal connection. Also layers should be the same between label and path.
 
Thank you for your support, it worked now. However still one pending issue tried to check what is wrong and still stuck.
Layout Net: 1 | Schematic Net: net1
==================+=================(sao 1)
Layout Net: 6 | OPEN
==================+======================

How to solve this one ?
 

Attachments

  • LVS Error1.png
    LVS Error1.png
    244 KB · Views: 149
  • LVS Error2.png
    LVS Error2.png
    216.4 KB · Views: 142

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