krshna
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i have built a majority circuit in cadence virtuoso which is basically implementing AB+BC+CA function of 3 variables A,B,C.
can anyone let me know if there are any provisions to calculate the below parameters using the cadence virtuoso IC610 tool?
parasitic capacitance of each node
propagation delay
slew rate
area occupied by this design
can anyone let me know if there are any provisions to calculate the below parameters using the cadence virtuoso IC610 tool?
parasitic capacitance of each node
propagation delay
slew rate
area occupied by this design