If LVS has passed well, there should principally not be any difference between schematic and layout circuit.
That was probably true in very old (let's say, 1 um and above) technologies.
But this is definitely not true for more or less advanced technologies.
As an example - in latest technologies (16/10/7nm), oscillation frequency can decrease by a factor of 2x to 3x due to parasitics (parasitic C but mainly parasitic R).
An indirect proof of my point is a presence of "parasitic extraction" step in IC design flow - why would you need it if there is no difference?
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deveshkm - post-layout simulations being significantly different form schematic simulation results is a common problem (especially in latest, FinFET technologies - 16nm, 14nm, 10nm, 7nm, 5nm, ...).
Usually this is caused by layout parasitics.
As a quick suggestion for debugging - do the extraction in different modes - 1. device only (no R or C - but with device instances having layout-dependent parameters), 2. C only, 3. R only, 4. full distributed RC.
Then run simulations for each, and see where the results start failing (significantly different from schematic simulations).
If you suspect this is caused by net / device mismatch - there are software tools that can detect and debug such mismatched (accounting for parasitics and layout-dependent effects) much more efficiently than trying to run post-layout simulations and then trying to make sense out of that.
I can help you with that.
Max