cadence pcb editor prolem

[karan29]

i am new to cadence . i go through various tutorials. i make one footprint in orcade pcb editor and save it as dra file at location
C:\Cadence\SPB_16.3\share\pcb\pcb_lib\symbols\ location.
when i open pcb editor and then open this foot print its look perfect as i created . but when i import through schematic made in orcade capture to pcb editor in board file its totally changed its pads are misaligned and size also changed
i cant find what is the problem?????
and for some component when i try to manually place error shone
W- (SPMHUT-127): Could not find pad stack SMD12_71-1
while i already save this pade to C:\Cadence\SPB_16.3\share\pcb\pcb_lib\symbols\ location.
please help me

 

[kabaleevisu]

hi karan,
go to setup-->user preference-->select the library-->select pad path and psm path give the pad path and footprint location.and import the netlist it willl work

 

[karan29]

hi karan,
go to setup-->user preference-->select the library-->select pad path and psm path give the pad path and footprint location.and import the netlist it willl work

i done but when i import logic it still shows warning and still my problem not resolved. here is netrv.lst file which i get
-----------------------------------------------------------------------

(---------------------------------------------------------------------)
( )
( Netrev Allegro Import Logic )
( )
( Drawing : rfidtag.brd )
( Software Version : 16.3p004 )
( Date/Time : Fri Dec 06 18:01:32 2013 )
( )
(---------------------------------------------------------------------)


------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'C:/Users/sys/Desktop/rfidtag';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'C:/Users/sys/Desktop/rfidtag/allegro/rfidtag.brd';
NEW_BOARD_NAME 'C:/Users/sys/Desktop/rfidtag/allegro/rfidtag.brd';

CmdLine: netrev -$ -i C:/Users/sys/Desktop/rfidtag -y 1 C:/Users/sys/Desktop/rfidtag/allegro/#Taaaaaa02788.tmp

------ Preparing to read pst files ------

Starting to read C:/Users/sys/Desktop/rfidtag/pstchip.dat
Finished reading C:/Users/sys/Desktop/rfidtag/pstchip.dat (00:00:00.09)
Starting to read C:/Users/sys/Desktop/rfidtag/pstxprt.dat
Finished reading C:/Users/sys/Desktop/rfidtag/pstxprt.dat (00:00:00.00)
Starting to read C:/Users/sys/Desktop/rfidtag/pstxnet.dat
Finished reading C:/Users/sys/Desktop/rfidtag/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------


#1 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH63_70' for device 'CAP_TH63_70_CAP': WARNING(SPMHUT-127): Could not find padstack TH63_70-1.

#2 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH70_78' for device 'CAP_TH70_78_CAP': WARNING(SPMHUT-127): Could not find padstack THP70_78-1.

#3 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH63_70' for device 'LED_TH63_70_LED': WARNING(SPMHUT-127): Could not find padstack TH63_70-1.

#4 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH63_70' for device 'DIODE TVS_TH63_70_DIODE TVS': WARNING(SPMHUT-127): Could not find padstack TH63_70-1.

#5 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH63_70' for device 'DIODE TS BI-DIR_TH63_70_DIODE T': WARNING(SPMHUT-127): Could not find padstack TH63_70-1.

#6 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH63_70' for device 'DIODE SCHOTTKY_TH63_70_DIODE SC': WARNING(SPMHUT-127): Could not find padstack TH63_70-1.

#7 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'TH63_70' for device 'DIODE SCHOTTKY_TH63_70_SCHOTTKY': WARNING(SPMHUT-127): Could not find padstack TH63_70-1.

#8 WARNING(SPMHNI-192): Device/Symbol check warning detected.

ERROR(SPMHNI-196): Symbol 'TWINCON' for device 'CONNECTOR TWINAX-J_TWINCON_CONN' has extra pin '0'.

ERROR(SPMHNI-196): Symbol 'TWINCON' for device 'CONNECTOR TWINAX-J_TWINCON_CONN' has extra pin '3'.

ERROR(SPMHNI-196): Symbol 'TWINCON' for device 'CONNECTOR TWINAX-J_TWINCON_CONN' has extra pin '4'.

#9 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'MSP430F2272NEW' for device 'MSP430F2272_MSP430F2272NEW_MSP4': WARNING(SPMHUT-127): Could not find padstack SMD1271-1.

#10 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'SN65HVD72' for device 'MAX485/SO_1_SN65HVD72_MAX485/SO': WARNING(SPMHUT-127): Could not find padstack SMD17_57S-1.

#11 WARNING(SPMHNI-192): Device/Symbol check warning detected.

WARNING(SPMHNI-337): Unable to load symbol 'MC34063' for device 'MC340632A_MC34063_MC340632A': WARNING(SPMHUT-127): Could not find padstack SMD20_55-1.

------ Library Paths ------
MODULEPATH = .
C:/Cadence/SPB_16.3/share/local/pcb/modules

PSMPATH = C:\Cadence\SPB_16.3\share\pcb\pcb_lib\symbols\

PADPATH = C:\Cadence\SPB_16.3\share\pcb\pcb_lib\symbols\


------ Summary Statistics ------


netrev run on Dec 6 18:01:32 2013
DESIGN NAME : 'RFIDTAG'
PACKAGING ON Nov 17 2009 03:09:43

COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON

No error detected
No oversight detected
11 warnings detected

cpu time 0:01:06
elapsed time 0:00:00
----------------------------------------------------------------------------------------------

i developed these pad using pad developer...

 

[wzhe6095]

u should draw a boundary first, then import the logical, it will work. Try it!

 

[vdalegro]

u should draw a boundary first, then import the logical, it will work. Try it!

Hello,

If I want to import netlist to the PCB file already create with boundary, should I create a new boundary before loading netlist ?

Thanks

 

[kabaleevisu]

if board outline already available no need to draw any thing .you can import the netlist directly

 

[vdalegro]

if board outline already available no need to draw any thing .you can import the netlist directly

Hello Kapil,

Thanks for reply.

I try to load a netlist file (*.MNL) that has been created from my own schematic to a PCB (that I got from Internet to try to modify a little from this PCB for my application).
When I use the inport logic, I got the error: "ERROR(SPMHA2-1): Line length overflow (1024 characters maximum) ... rest of line ignored".

Do you know what happens ?

Do you have any idea for this kink of modification ?


Thanks for your helps




===========================================================



^
ERROR(SPMHA2-1): Line length overflow (1024 characters maximum) ... rest of li~
ne ignored.
-------------------------------------------------------------------------------



===========================================================
Starting gate assignment. Fri Feb 13 09:24:04 2015

Assigning gates of drawing P:/Publique/Electrical/Engineering/QLINK-100001/PCB/QLNK-100001.brd

Gates of differing rooms will not be assigned to the same component.

Gate assignment will use empty slots in existing components.


STEP I


STEP II

Finished with gate assignment. Fri Feb 13 09:24:04 2015

===========================================================

===========================================================
End of NETLIST IN Syntax/Logic Check
===========================================================

Total Netlist Warnings = 0.
Total Netlist Errors = 1.

===========================================================

Total Combined Netlist and Device File Warnings = 0.
Total Combined Netlist and Device File Errors = 1.

===========================================================
End of Allegro NETLIST IN Log
===========================================================

 

[kabaleevisu]

Hi,
i could not understand clearly but if you follow the step it may be import
1.open the library and then edit the padstack (simply open and save it)
2.check your library should be assign the path or not (i replied already)
3.open PCB editor and set the pad path and psm path and then draw board outline (class:board geometry and subclassutline)
3.Generate the netlist and import the netlist in PCB Editor (file-->import-->Logic-->select the path of the net list )
4.after that place-->quick place-->ok
5.now check any footprint are imported or not
6.if you got any error in between check the file-->viewlog
post that error i will try to help u

 

[vdalegro]

Hi,
i could not understand clearly but if you follow the step it may be import
1.open the library and then edit the padstack (simply open and save it)
2.check your library should be assign the path or not (i replied already)
3.open PCB editor and set the pad path and psm path and then draw board outline (class:board geometry and subclassutline)
3.Generate the netlist and import the netlist in PCB Editor (file-->import-->Logic-->select the path of the net list )
4.after that place-->quick place-->ok
5.now check any footprint are imported or not
6.if you got any error in between check the file-->viewlog
post that error i will try to help u

Thanks for explanation step-by-step to import netlist to a NEW PCB file. That is OK for me. But my problem is a little different.

To clarify my problem, I have a post here: https://www.edaboard.com/threads/332064/

Thanks for helps