Cadence layout problem in LVS

[bestvlsi]

Hi All,

I am doing layout for an NMOS differential pair with PMOS active load . The differential pair layout has passed the DRC and LVS. The PMOS active load has passed the DRC but is stuck with LVS.

The problem I am facing in LVS is that its throwing up an error that the width of one of the devices is more than that of the other.

After checking the log file i found that in Reduce statistics Cadence has reduced the number of PMOS transistor to 1.

Reduce Statistics
================= Filtered Reduced
Cell/Device schematic layout schematic layout
(N_18_MM) MOS 2 4* 2 2
(P_18_MM) MOS 3 5* 1 1
(P_18_MMarMos2#1) MosBlk - - 1 1

Also there is 1 PMOS used for powerdown facility in the current mirror load.

Now each of the PMOS and NMOS device has 2 fingers as well as 2 dummy for the differential pair and active current mirror load, respectively . Now why does the reduced schematic has only 1 PMOS transistor instead
of 3 ( the 2 active loads and 1 power down) .

Also the log file is as given in the attachment below.

And the layout is shown in the attachment.


Regards.

 

[jimito13]

Are you sure that the PMOS' layout dimensions correspond to the schematic's?Start from this.
Also you can try to delete the pmos instances from layout (without the routing lines) and bring them back inside and then put them back to their position.
Re-run LVS and if the problem persists maybe there is an issue with the function that handles the interdigitized devices and the devices with fingers (See the message in the log file that mentions about merged devices).

 

[bestvlsi]

Hi jimito13,

Thanks for the reply . i had a discussion with my colleagues regarding the necessity of dummy transistors for active loads ... and they too agreed with my point of view that for the active current loads we need not go for the dummy devices... which are creating this problem ... since this differential amplifier is the first stage of an opamp which is not fully differential....so I am going to remove the dummies from the PMOS active loads.

Moreover moving to the solution given by you ... the last point which you mentioned regarding the "function that handles the interdigitized devices" can u pls elaborate on how to check the function which handles this particular case...

Thanks a lot bro and a happy new year.

Regards

---------- Post added at 15:15 ---------- Previous post was at 15:02 ----------

Hi all

I did try without dummy but it still giving same error .. Any other idea why this error is coming .

Regards

 

[erikl]

Now each of the PMOS ... device has 2 fingers

Are you sure that the PMOS' layout dimensions correspond to the schematic's?

Estimating from your layout dimensions, I think each of your differential PMOSes actually has a total width of 12µm only, whereas your schematic states a total of w=24µm per PMOS.