rojyar_2020
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I meet thease DRC errors in my Layout in cadence
1. off grid polygon in layer poly, NIMP or...
2.figure having no stamped connectionS.
N+SD to Psub tap spacing must be <=10u
it should be mentioned that thease errors occur even i draw only one transistor using its standard library (create->instance)
I use IC5141 and 0.18um GPDK cadence technology file. please help.
1. off grid polygon in layer poly, NIMP or...
2.figure having no stamped connectionS.
N+SD to Psub tap spacing must be <=10u
it should be mentioned that thease errors occur even i draw only one transistor using its standard library (create->instance)
I use IC5141 and 0.18um GPDK cadence technology file. please help.
