burst fron one clock domain to another

[sun_ray]

A burst of length 6 with each data width one is coming from one clock domain and the burst need to be transferred to a new asynchronous clock domain. Can you please provide a way other than using a FIFO?

 

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use multiple 6-bit registers and cycle through them for writing. read the register contents in the new clock domain when they are not being accessed by the write logic. Depending on the relationship between the two clock frequencies you may need only two 6-bit registers or a whole bunch of them.

Instead of registers you could use a dual port memory and have multiple 6-bit queues and cycle through them, but then that is more or less a FIFO.

 

[sun_ray]

use multiple 6-bit registers and cycle through them for writing. read the register contents in the new clock domain when they are not being accessed by the write logic. Depending on the relationship between the two clock frequencies you may need only two 6-bit registers or a whole bunch of them.

But when you read the registers in the new clock domain, metastability will happen. Is not it? Can you please draw a diagram of the whole circuit to understand it more.

What do you want to mean by "Depending on the relationship between the two clock frequencies you may need only two 6-bit registers or a whole bunch of them"? Can you please explain more on this?

Regardrs

 

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But when you read the registers in the new clock domain, metastability will happen. Is not it?

Then you don't understand metastability and how to deal with it. (This is one of the first questions I ask a job interviewee)

If you capture the contents of the register in the new clock domain while any of the bits are being updated and that change is within the setup and hold time of the capturing register. The register may or may not go metastable. I'm suggesting the register should be captured between updates when it's stable.

Can you please draw a diagram of the whole circuit to understand it more.

No, I do this on my own time as a courtesy to the community. If I have to design circuits for someone that is "work" and I get paid for doing "work".

What do you want to mean by "Depending on the relationship between the two clock frequencies you may need only two 6-bit registers or a whole bunch of them"? Can you please explain more on this?

If the clock domain the serial burst is coming from is faster than the second clock domain and there is the possibility of multiple bursts occurring at irregular intervals (aggregate rate of writes must be equal to or less than the read side, otherwise you will eventually overwrite data that has not been read), then there must be multiple 6-bit registers to capture the multiple 6-bit bursts so you have time to capture the data on the read side. As the clock rate is lower on the read side you need more time to read 6-bits than to write them. e.g. if wr_clk is 200 MHz and rd_clk is 100 MHz it takes 30ns to write and 60ns to read each bit. If you perform 4 back to back writes then it takes 120ns to write all 4 registers and 240ns to read all four registers. As you can see there has to be some limit to the sustained write burst, otherwise you can never transfer the data between the two clock domains.

I think you need to start reading about metastablility and asynchronous clock domains. There are a lot of papers written on this subject that you could read.

 

[sun_ray]

Then you don't understand metastability and how to deal with it. (This is one of the first questions I ask a job interviewee)

I need to correct you here. I understand metastability well and also the asynchronous clock domains.

No, I do this on my own time as a courtesy to the community. If I have to design circuits for someone that is "work" and I get paid for doing "work".

I understand this. But your circuit is not very clear till now. A diagram can represent the circuit well. Do you want the implementation as shift register?

Sorry for the delayed reply.

Regards