CMOS, on insulating handle wafer. Some foundries have
common frontside processing and a choice of plain, epi
or thick film SOI (like TowerJazz CA18). I do not know
what C05 offers or why you want to independently bias
device bodies.
I have used CA18HB which has 5V devices and is SOI.
There are about 20 CA18 flow variants, maybe 4 of them
SOI. I've even gotten SOI mixed in with JI wafers on the
multiproject runs.
Check with your foundry about flow variants. Who sets
the technology, anyway?
2) redesign the circuit accounting for Vsb being not zero.
Yes. For the bunch of flying NMOS transistors where sources are not connected to gnd you could use native NFETs (Vth≈0). As they are stacked at positions higher than gnd, they can easily be closed down (OFF), and also don't need much more gate control voltage for the ON state than their normal NFET brothers (Vth>0).
For stacked PMOS transistors it's no pb. anyway, they just need their own nwells (which are connected to the respective source).
EPI wafers use a very low-resistive substrate with a thin epitaxially grown layer on it, of the same doping type, but with higher resistivity. This is the actual (NMOS) substrate. Because of the additional EPI process, they are bit more expensive than non-EPI wafers, but offer better EMI and noise isolation between different (guard-ringed) blocks.
If C5 has an option for native NMOSFETs, they will offer an extra schematic view for them, as well as simulation, and (pCell) layout and abstract views. May be native NMOSFETs are limited to larger min. W & L bounds than the normal NMOSFETs. If 5V native NMOSFETs are available, you should find out from your PDK description. I've never seen such.... would you advise how to layout the native NMOS transistor? Also, in the schematic view is there a way to specify them instead of normal NMOS?
Can these native transistor withstand with 5V voltages or they are weak?
For each flying PMOSFET you need an extra n-well. In this n-well you connect its ntaps (n+ diffusion in n-well) to the PMOSFET's source, so you get Vsb=0. That's it!So you mean add nwells is different than ntap?
I guess EPI wafers are standard nowadays. Standard is high volume, by that may be cheaper.... strangely they wrote for non-EPI option you need to pay more.
If C5 has an option for native NMOSFETs, they will offer an extra schematic view for them, as well as simulation, and (pCell) layout and abstract views. May be native NMOSFETs are limited to larger min. W & L bounds than the normal NMOSFETs. If 5V native NMOSFETs are available, you should find out from your PDK description. I've never seen such.
For each flying PMOSFET you need an extra n-well. In this n-well you connect its ntaps (n+ diffusion in n-well) to the PMOSFET's source, so you get Vsb=0. That's it!
... do think Transmission Gate (nMOS+pMOS) switch would be better option for flying switches? So, if native nMOS not supported, TG can work better than normal nMOS?
For "flying" switches not necessarily native nMOS are needed - again this depends on voltage levels to be switched, and if your control voltage range is adequate for this.
I like the option of native nMOS so I can take rid of the body effect.
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