biasing
The process in that papar is 0.18um 1P6M, be careful, next part is the most interesting part, "triple well." I have no idea what "triple well" means, N-well, P-well, and what's next?
The reason people keep telling you that you can't do bulk biasing for NMOS is that there are few process providing P-well mask. Couple years ago, many processes got "twin-well," means N-well and P-well, you can do any bulk biasing on any particular transistor in that kind of process. However, manufacturing companies stopped making P-well to reduce cost, I think, because you don't need the P-well mask anymore.
So, nowaday, the manufacturing company make it more like P-well all chip wide unless you define some area as N-well. So the area outside N-wells can be treated as a big P-well and it has only one well contact and it has to be connected to the single voltage. That's why you can't bulk biasing the NMOS separetely because their bulk all connected together. You want bulk biasing the NMOS, bulk biasing all the NMOS transistors together.
Unless you can find a process that got P-well for NMOS, you can't do any bulk biasing on NMOS. I don't think the process used in that paper is TSMC 0.18um process.