Built in self test with multiple scanning

[jincyjohnson]

whether ISCAS benchmark circuits are combinational or sequential.if they are combinational then how can we use scan based testing with BIST.In scan based testing with BIST whether the scanning flip flop is the flip flop already available in the benchmark circuit.In multiple scan testing, how the number of scan chains is fixed.

 

[rca]

Well, same remark, what to you want?
BIST is Build in self test, means logic added to check macros/logic.
a Bist to check the logic will be memory consumming, because you need to save the stimulus patterns and the result patterns to know if the logic is clean.
BIST is generally associated to memory.
The scan chain number is determined by the number of pads available.
You could also have the scan compression technique, and the tool will indicate the compression ratio usefull for your design.

 

[jincyjohnson]

what is meant by number of pads and scan compression technique.what is the advantage of BIST compared to boundary scan.can u please explain the scan method of testing

 

[maulin sheth]

Hello,
There is not any comparison between BIST and boundary scan as both purpose is different.

I suggest you that you just need to go through the basics of DFT first....You will get the lots of material on basics of DFT through net.

 

[jincyjohnson]

normally the gate level netlist of ISCAS 85 and ISCAS 89 are available as verilog code.can we change this automatically to vhdl using some softwares

 

[rca]

BIST is build in self-test, means logics added to control/check macros/memories.
Boundary Scan is additional logic to check the connection inter chips on the PCB.