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Do you know what OUTP and OUTN are connected to? I see two identical inputs with two outputs. I'd guess that like bipolar devices, PMOS handle input signals almost down to 'gnd' whereas NMOS wouldn't begin to conduct input signal until it is above VGS(th).
And, when Vin = 0, Vout = 0 as INP (or INN) sinks the current from the PMOS connected to it from the current source so compared to the load impedance, INP is the path of least resistance to 'gnd'. When Vin = 1, Vout = 1 because INP is off and high impedance so the current (or voltage, depending on which is of most interest) from the current source transistor flows to load.
What is it you are specifically asking, if (presumably) it hasn't been answered by this reply?
Also, we can hope that the gate is a high impedance input (good for the lower impedance source) and the drain/source output is low impedance (good for the ideally higher impedance load).
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