bringing block level sdc to top level

[rocking_vlsi]

Hi

I have two sdc files which are generated for two different blocks independently.

Can I use them for synthesizing top level design which contain those two blocks?

 

[sun_ray]

Hi

I have two sdc files which are generated for two different blocks independently.

Can I use them for synthesizing top level design which contain those two blocks?

You take one of them and add feature in that relevant to the other block/sdc. You need to make one SDC for synthesizing both of them.

 

[Manochitra]

hi...

I think u can synthesize using two different sdc's ...but the thing is clock given for two blocks should not be same ... I have tried with two different sdc's for single block which has two different functionalities..

 

[sun_ray]

Manochitra

In this case the if two SDCs are used the SDCs needs changes to synthesize the block. So it is better to make one SDC instead of two fur synthesizing the two blocks.

Regards

 

[dftrtl]

There are tools to convert block level constraints to top level constraints like fishtail.

 

[lohi21]

Has the 2 blocks PNR completed? If yes, Has the ETM models generated by the PT/sign off tool? If done, then most of the information is available at the .lib's of your blocks and write out correct SDC at the top level by giving correct number for set_input_delay and so..

This would generated faster optimizations at the top level,

if any of the above has not completed, then yes u can use both the sdc's and make sure to have correct clock definations and synthesis at the top level, Don't forget to group it at top.

 

[vijayR15]

Hi rocking_vlsi,

u can do with two sdc.., also u can do with a single sdc..,,

u will not c much difference with having number of sdc..,