FlyingDutch
Advanced Member level 1
- Joined
- Dec 16, 2017
- Messages
- 457
- Helped
- 45
- Reputation
- 92
- Reaction score
- 55
- Trophy points
- 28
- Location
- Bydgoszcz - Poland
- Activity points
- 4,958
NET "Clk100Mhz1" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz ;
NET "Clk100Mhz2" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz ;
NET "io_asyncReset" LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; #SW1
NET "io_jtag_tms" LOC = U7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 1
NET "IO_P6[6]" LOC = V7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 2
NET "IO_P6[5]" LOC = T4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 3
NET "IO_P6[4]" LOC = V4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4
NET "io_sdram_ADDR[0]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[10]" LOC = F4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[11]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[12]" LOC = G6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[1]" LOC = J6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[2]" LOC = H5 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[3]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[4]" LOC = F3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[5]" LOC = H4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[6]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[7]" LOC = H6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[8]" LOC = D2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[9]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[0]" LOC = F2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[1]" LOC = F1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_read[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DQ_write[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
1. In the HDL source code. Example in VHDL:
io_sdram_DQ_read <= mcb_dram_dq;
mcb_dram_dq <= io_sdram_DQ_write when io_sdram_DQ_writeEnable = '1' else "ZZZZZZZZZZZZZZZZ";
.
But this functionality must be handled by SDRAM memory controller -- and after synthesis a proper bi-dir macro should be placed.
It is handled by the SDRAM memory controller, via the signal "io_sdram_DQ_writeEnable". To get maximum flexibility for implementation in FPGA's and ASIC's, you should never have bidirectional ports on an IP block.
The BrieySOC does this the correct way, separate ports for in and out, and a special signal that controls the direction of the pins.
The bidirectional buffers should be placed by the user in the top level, and both the methods I listed will work for FPGA's. For ASIC's you want to instantiate the bidirectional primitives explicitly (method 2).
The bidirectional buffers should be placed by the user in the top level, and both the methods I listed will work for FPGA's.
/* Top module: Briey SOC */
module BrieySOC(
input io_asyncReset,
input Clk100Mhz,
input io_jtag_tms,
input io_jtag_tdi,
output io_jtag_tdo,
input io_jtag_tck,
output [12:0] io_sdram_ADDR,
output [1:0] io_sdram_BA,
//input [15:0] io_sdram_DQ_read,
//output [15:0] io_sdram_DQ_write,
inout [15:0] io_sdram_DATA,
output io_sdram_DQ_writeEnable,
output [1:0] io_sdram_DQM,
output io_sdram_CASn,
output io_sdram_CKE,
output io_sdram_CSn,
output io_sdram_RASn,
output io_sdram_WEn,
input [3:0] io_gpioA_read,
output [3:0] io_gpioA_write,
output [3:0] io_gpioA_writeEnable,
output io_uart_txd,
input io_uart_rxd,
output io_vga_vSync,
output io_vga_hSync,
output io_vga_colorEn,
output [4:0] io_vga_color_r,
output [5:0] io_vga_color_g,
output [4:0] io_vga_color_b,
input io_timerExternal_clear,
input io_timerExternal_tick,
input io_coreInterrupt
);
//----------------------------------------------------
//-- Connecting wires
wire clkAXIOut;
wire clkLOCKED;
wire clkVGAOut;
wire clkBuf100MHz;
wire clkForward100MHz;
wire CLK_TO_PINS;
wire TRISTATE_OUTPUT;
wire CLK_RESET;
wire [15:0] io_sdram_DQ_read;
wire [15:0] io_sdram_DQ_write;
CLKWizard CLKGEN
(// Clock in ports
.CLK_IN1(Clk100Mhz),
// Clock out ports
.CLK_OUT1(clkAXIOut), //50 MHz AXI clock
.CLK_OUT2(clkVGAOut), //25.175 MHz VGA clock
.CLK_OUT3(clkBuf100MHz), //100 MHz DDR memory clock
// Status and control signals
.RESET(io_asyncReset),
.LOCKED(clkLOCKED));
//---- DDR memory bufer bi-directional ---------
BiDirBuffer DDRDataBuffer
(
.DATA_TO_AND_FROM_PINS(io_sdram_DATA), //Bi-Directional pins
.DATA_IN_TO_DEVICE(io_sdram_DQ_read), //Output pins
// From the device out to the system
.DATA_OUT_FROM_DEVICE(io_sdram_DQ_write), //Input pins
.CLK_TO_PINS(CLK_TO_PINS), //Output pins
.TRISTATE_OUTPUT(TRISTATE_OUTPUT), //Input pin
.CLK_IN(clkBuf100MHz), // Single ended clock from IOB
.CLK_OUT(clkForward100MHz), //Fast clock ouput
.CLK_RESET(io_asyncReset), //clocking logic reset
.IO_RESET(io_asyncReset) //system reset
);
//---- CPU instance ---------
Briey SoC(
.io_asyncReset(io_asyncReset),
.io_axiClk(clkAXIOut),
.io_vgaClk(clkVGAOut),
.io_jtag_tms(io_jtag_tms),
.io_jtag_tdi(io_jtag_tdi),
.io_jtag_tdo(io_jtag_tdo),
.io_jtag_tck(io_jtag_tck),
.io_sdram_ADDR(io_sdram_ADDR),
.io_sdram_BA(io_sdram_BA),
.io_sdram_DQ_read(io_sdram_DQ_read),
.io_sdram_DQ_write(io_sdram_DQ_write),
.io_sdram_DQ_writeEnable(io_sdram_DQ_writeEnable),
.io_sdram_DQM(io_sdram_DQM),
.io_sdram_CASn(io_sdram_CASn),
.io_sdram_CKE(io_sdram_CKE),
.io_sdram_CSn(io_sdram_CSn),
.io_sdram_RASn(io_sdram_RASn),
.io_sdram_WEn(io_sdram_WEn),
.io_gpioA_read(io_gpioA_read),
.io_gpioA_write(io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_uart_txd),
.io_uart_rxd(io_uart_rxd),
.io_vga_vSync(io_vga_vSync),
.io_vga_hSync(io_vga_hSync),
.io_vga_colorEn(io_vga_colorEn),
.io_vga_color_r(io_vga_color_r),
.io_vga_color_g(io_vga_color_g),
.io_vga_color_b(io_vga_color_b),
.io_timerExternal_clear(io_timerExternal_clear),
.io_timerExternal_tick(io_timerExternal_tick),
.io_coreInterrupt(io_coreInterrupt)
);
endmodule
//input [15:0] io_sdram_DQ_read,
//output [15:0] io_sdram_DQ_write,
inout [15:0] io_sdram_DATA,
NET "Clk100Mhz" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz ;
NET "io_asyncReset" LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; #SW1
NET "io_jtag_tms" LOC = U7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 1
NET "io_jtag_tdi" LOC = V7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 2
NET "io_jtag_tdo" LOC = T4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 3
#NET "io_jtag_tck" LOC = V4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4
NET "io_sdram_ADDR[0]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[10]" LOC = F4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[11]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[12]" LOC = G6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[1]" LOC = J6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[2]" LOC = H5 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[3]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[4]" LOC = F3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[5]" LOC = H4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[6]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[7]" LOC = H6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[8]" LOC = D2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[9]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[0]" LOC = F2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[1]" LOC = F1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
ERROR:NgdBuild:770 - IBUFG 'DDRDataBuffer/ibufg_clk_inst' and BUFG
'CLKGEN/clkout3_buf' on net 'clkBuf100MHz' are lined up in series. Buffers of
the same direction cannot be placed in series.
ERROR:NgdBuild:924 - input pad net 'clkBuf100MHz' is driving non-buffer
primitives:
Something is wrong with the design. Where is the differential DDR clock to the SDRAM? I can't see it from the sdram controller.
You must drive all signals to the SDRAM.
Your ucf file is missing DDR_UDQS, DDR-LDQS, DDR-CK_P, DDR-CK_N, DDR-CKE, DDR-WE, DDR-CAS, DDR-RAS, DDR-UDM, DDR-LDM.
The CS signal on the SDRAM can't be driven from the FPGA since it is grounded via a resistor on the PCB.
You have added a DDR register, but that is only correct if the DDR registers are not included in the sdram controller. I can't tell if your sdram controller has internal DDR registers or not.
Have you generated the sdram controller yourself?
If the DDR registers are not inside the sdram controller, the number of data lines on the controller must be twice as many as on the external memory.
You must find out what should drive the differential clock (DDR-CK_P and DDR-CK_N). Then we will know more.
The error message is about the clock, but there is no meaning to work on that until we know if the DDR register is needed, and until we have found the clock to the SDRAM.
You forgot to connect the signal that must control the data direction, it is "io_sdram_DQ_writeEnable".
/* Top module: Briey SOC */
module BrieySOC(
input io_asyncReset,
input Clk100Mhz,
input io_jtag_tms,
input io_jtag_tdi,
output io_jtag_tdo,
input io_jtag_tck,
output [12:0] io_sdram_ADDR,
output [1:0] io_sdram_BA,
//input [15:0] io_sdram_DQ_read,
//output [15:0] io_sdram_DQ_write,
inout [15:0] io_sdram_DATA,
output io_sdram_DQ_writeEnable,
output [1:0] io_sdram_DQM,
output io_sdram_CASn,
output io_sdram_CKE,
output io_sdram_CSn,
output io_sdram_RASn,
output io_sdram_WEn,
input [3:0] io_gpioA_read,
output [3:0] io_gpioA_write,
output [3:0] io_gpioA_writeEnable,
output io_uart_txd,
input io_uart_rxd,
output io_vga_vSync,
output io_vga_hSync,
output io_vga_colorEn,
output [4:0] io_vga_color_r,
output [5:0] io_vga_color_g,
output [4:0] io_vga_color_b,
input io_timerExternal_clear,
input io_timerExternal_tick,
input io_coreInterrupt
);
//----------------------------------------------------
//-- Connecting wires
wire clkAXIOut;
wire clkLOCKED;
wire clkVGAOut;
wire clkBuf100MHz;
wire clkDDR100MHz;
wire clkForward100MHz;
wire CLK_TO_PINS;
wire TRISTATE_OUTPUT;
wire CLK_RESET;
wire [15:0] io_sdram_DQ_read;
wire [15:0] io_sdram_DQ_write;
CLKWizard CLKGEN
(// Clock in ports
.CLK_IN1(Clk100Mhz),
// Clock out ports
.CLK_OUT1(clkAXIOut), //50 MHz AXI clock
.CLK_OUT2(clkVGAOut), //25.175 MHz VGA clock
.CLK_OUT3(clkBuf100MHz), //100 MHz DDR memory clock
// Status and control signals
.RESET(io_asyncReset),
.LOCKED(clkLOCKED));
//---- DDR memory bufer bi-directional ---------
BiDirBuffer DDRDataBuffer
(
.DATA_TO_AND_FROM_PINS(io_sdram_DATA), //Bi-Directional pins
.DATA_IN_TO_DEVICE(io_sdram_DQ_read), //Output pins
// From the device out to the system
.DATA_OUT_FROM_DEVICE(io_sdram_DQ_write), //Input pins
.CLK_TO_PINS(CLK_TO_PINS), //Output pins
.TRISTATE_OUTPUT(TRISTATE_OUTPUT), //Input pin
.CLK_IN(clkBuf100MHz), // Fast clock input from PLL/MMCM
.LOCKED_IN(clkLOCKED), //Input pin
.LOCKED_OUT(LOCKED_OUT), //Output pin
.CLK_RESET(CLK_RESET), //clocking logic reset
.IO_RESET(io_asyncReset) //system reset
);
//---- CPU instance ---------
Briey SoC(
.io_asyncReset(io_asyncReset),
.io_axiClk(clkAXIOut),
.io_vgaClk(clkVGAOut),
.io_jtag_tms(io_jtag_tms),
.io_jtag_tdi(io_jtag_tdi),
.io_jtag_tdo(io_jtag_tdo),
.io_jtag_tck(io_jtag_tck),
.io_sdram_ADDR(io_sdram_ADDR),
.io_sdram_BA(io_sdram_BA),
.io_sdram_DQ_read(io_sdram_DQ_read),
.io_sdram_DQ_write(io_sdram_DQ_write),
.io_sdram_DQ_writeEnable(io_sdram_DQ_writeEnable),
.io_sdram_DQM(io_sdram_DQM),
.io_sdram_CASn(io_sdram_CASn),
.io_sdram_CKE(io_sdram_CKE),
.io_sdram_CSn(io_sdram_CSn),
.io_sdram_RASn(io_sdram_RASn),
.io_sdram_WEn(io_sdram_WEn),
.io_gpioA_read(io_gpioA_read),
.io_gpioA_write(io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_uart_txd),
.io_uart_rxd(io_uart_rxd),
.io_vga_vSync(io_vga_vSync),
.io_vga_hSync(io_vga_hSync),
.io_vga_colorEn(io_vga_colorEn),
.io_vga_color_r(io_vga_color_r),
.io_vga_color_g(io_vga_color_g),
.io_vga_color_b(io_vga_color_b),
.io_timerExternal_clear(io_timerExternal_clear),
.io_timerExternal_tick(io_timerExternal_tick),
.io_coreInterrupt(io_coreInterrupt)
);
endmodule
`timescale 1ns / 1ps
/* Top module: Briey SOC */
module BrieySOC(
input io_asyncReset,
input Clk100Mhz,
input io_jtag_tms,
input io_jtag_tdi,
output io_jtag_tdo,
input io_jtag_tck,
output [12:0] io_sdram_ADDR,
output [1:0] io_sdram_BA,
//input [15:0] io_sdram_DQ_read,
//output [15:0] io_sdram_DQ_write,
inout [15:0] io_sdram_DATA,
output io_sdram_DQ_writeEnable,
output [1:0] io_sdram_DQM,
output io_sdram_CASn,
output io_sdram_CKE,
output io_sdram_CSn,
output io_sdram_RASn,
output io_sdram_WEn,
output io_sdram_clk,
output io_sdram_clk_n,
input [3:0] io_gpioA_read,
output [3:0] io_gpioA_write,
output [3:0] io_gpioA_writeEnable,
output io_uart_txd,
input io_uart_rxd,
output io_vga_vSync,
output io_vga_hSync,
output io_vga_colorEn,
output [4:0] io_vga_color_r,
output [5:0] io_vga_color_g,
output [4:0] io_vga_color_b,
input io_timerExternal_clear,
input io_timerExternal_tick,
input io_coreInterrupt
);
//----------------------------------------------------
//-- Connecting wires
wire clkAXIOut;
wire clkLOCKED;
wire clkVGAOut;
wire clkBuf100MHz;
wire clkDDR100MHz;
wire clkJTAGBuf;
wire CLK_TO_PINS;
wire TRISTATE_OUTPUT;
wire CLK_RESET;
wire [15:0] io_sdram_DQ_read;
wire [15:0] io_sdram_DQ_write;
CLKWizard CLKGEN
(// Clock in ports
.CLK_IN1(Clk100Mhz),
// Clock out ports
.CLK_OUT1(clkAXIOut), //50 MHz AXI clock
.CLK_OUT2(clkVGAOut), //25.175 MHz VGA clock
.CLK_OUT3(clkBuf100MHz), //100 MHz DDR memory clock
// Status and control signals
.RESET(io_asyncReset),
.LOCKED(clkLOCKED));
//Input buffer for JTAG in clock
IBUFG IBUFG_01
(
.O(clkJTAGBuf),
.I(io_jtag_tck)
);
//Output buffer for DDR diff clock (out)
OBUFDS #(
.IOSTANDARD("DIFF_MOBILE_DDR")
) OBUFDS_01 (
.O(io_sdram_clk),
.OB(io_sdram_clk_n),
.I(clkBuf100MHz)
);
//---- DDR memory bufer bi-directional ---------
BiDirBuffer DDRDataBuffer
(
.DATA_TO_AND_FROM_PINS(io_sdram_DATA), //Bi-Directional pins
.DATA_IN_TO_DEVICE(io_sdram_DQ_read), //Output pins
// From the device out to the system
.DATA_OUT_FROM_DEVICE(io_sdram_DQ_write), //Input pins
.CLK_TO_PINS(CLK_TO_PINS), //Output pins
.TRISTATE_OUTPUT(TRISTATE_OUTPUT), //Input pin
.CLK_IN(clkBuf100MHz), // Fast clock input from PLL/MMCM
.LOCKED_IN(clkLOCKED), //Input pin
.LOCKED_OUT(LOCKED_OUT), //Output pin
.CLK_RESET(CLK_RESET), //clocking logic reset
.IO_RESET(io_asyncReset) //system reset
);
//---- CPU instance ---------
Briey SoC(
.io_asyncReset(io_asyncReset),
.io_axiClk(clkAXIOut),
.io_vgaClk(clkVGAOut),
.io_jtag_tms(io_jtag_tms),
.io_jtag_tdi(io_jtag_tdi),
.io_jtag_tdo(io_jtag_tdo),
.io_jtag_tck(clkJTAGBuf),
.io_sdram_ADDR(io_sdram_ADDR),
.io_sdram_BA(io_sdram_BA),
.io_sdram_DQ_read(io_sdram_DQ_read),
.io_sdram_DQ_write(io_sdram_DQ_write),
.io_sdram_DQ_writeEnable(io_sdram_DQ_writeEnable),
.io_sdram_DQM(io_sdram_DQM),
.io_sdram_CASn(io_sdram_CASn),
.io_sdram_CKE(io_sdram_CKE),
.io_sdram_CSn(io_sdram_CSn),
.io_sdram_RASn(io_sdram_RASn),
.io_sdram_WEn(io_sdram_WEn),
.io_gpioA_read(io_gpioA_read),
.io_gpioA_write(io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(io_uart_txd),
.io_uart_rxd(io_uart_rxd),
.io_vga_vSync(io_vga_vSync),
.io_vga_hSync(io_vga_hSync),
.io_vga_colorEn(io_vga_colorEn),
.io_vga_color_r(io_vga_color_r),
.io_vga_color_g(io_vga_color_g),
.io_vga_color_b(io_vga_color_b),
.io_timerExternal_clear(io_timerExternal_clear),
.io_timerExternal_tick(io_timerExternal_tick),
.io_coreInterrupt(io_coreInterrupt)
);
endmodule
#---------------------------------------------------
NET "Clk100Mhz" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz ;
NET "io_asyncReset" LOC = M18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP; #SW1
###################################################################################################################################################
# HEADER P6 #
###################################################################################################################################################
NET "io_jtag_tms" LOC = U7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 1 Header P6
NET "io_jtag_tdi" LOC = V7 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 2
NET "io_jtag_tdo" LOC = T4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 3
#NET "io_jtag_tck" LOC = V4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4 - issue
#-------------------------- LPDDR RAM START--------------------------------------------------------------------
#NET "calib_done" LOC = P15 | IOSTANDARD = LVCMOS33;
#NET "error" LOC = P16 | IOSTANDARD = LVCMOS33;
#NET "c3_sys_rst_n" LOC = L15 | IOSTANDARD = LVCMOS33 | PULLDOWN; # Pin 7 of Header P9
NET "io_sdram_ADDR[0]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[10]" LOC = F4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[11]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[12]" LOC = G6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[1]" LOC = J6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[2]" LOC = H5 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[3]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[4]" LOC = F3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[5]" LOC = H4 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[6]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[7]" LOC = H6 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[8]" LOC = D2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_ADDR[9]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[0]" LOC = F2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_BA[1]" LOC = F1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_clk" LOC = G3 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "io_sdram_clk_n" LOC = G1 | IOSTANDARD = DIFF_MOBILE_DDR;
NET "io_sdram_DATA[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_DATA[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_CASn" LOC = K5 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_CKE" LOC = H7 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_RASn" LOC = L5 | IOSTANDARD = MOBILE_DDR;
NET "io_sdram_WEn" LOC = E3 | IOSTANDARD = MOBILE_DDR;
#-------------------------- LPDDR RAM END --------------------------------------------------------------------
##################################################################################################################################################
# HEADER P7 #
###################################################################################################################################################
NET "io_gpioA_read[0]" LOC = U8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 1
NET "io_gpioA_read[1]" LOC = V8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 2
NET "io_gpioA_read[2]" LOC = R8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 3
NET "io_gpioA_read[3]" LOC = T8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4
NET "io_gpioA_write[0]" LOC = R5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 5
NET "io_gpioA_write[1]" LOC = T5 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 6
NET "io_gpioA_write[2]" LOC = T9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 7
NET "io_gpioA_write[3]" LOC = V9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 8
###################################################################################################################################################
# HEADER P8 #
###################################################################################################################################################
NET "io_gpioA_writeEnable[0]" LOC = R11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 1
NET "io_gpioA_writeEnable[1]" LOC = T11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 2
NET "io_gpioA_writeEnable[2]" LOC = R10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 3
NET "io_gpioA_writeEnable[3]" LOC = T10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4
NET "io_vga_colorEn" LOC = U13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 5 : VGA output
NET "io_timerExternal_clear" LOC = V13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 6 : Ext. timer
NET "io_timerExternal_tick" LOC = U11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 7 : Ext. timer
NET "io_coreInterrupt" LOC = V11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 8 : Ext. interrupt
###################################################################################################################################################
# UART Interface #
###################################################################################################################################################
NET "io_uart_txd" LOC = A8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_uart_rxd" LOC = B8 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
###################################################################################################################################################
# VGA - less color resolution than in Briey #
###################################################################################################################################################
NET "io_vga_hSync" LOC = B12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_vSync" LOC = A12 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_r[4]" LOC = C9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_r[3]" LOC = B9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_r[2]" LOC = A9 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_g[5]" LOC = C11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_g[4]" LOC = A10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_g[3]" LOC = C10 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_b[4]" LOC = A11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "io_vga_color_b[3]" LOC = B11 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
#NET "io_jtag_tck" LOC = V4 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ; #Pin 4 - issue
Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair.
The clock IOB component <io_jtag_tck> is placed at site <T5>. The corresponding BUFG component <clkJTAGBuf_BUFG> is placed at site <BUFGMUX_X2Y10>.
There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used.
You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design,
you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue.
However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this erro...
NOTE: This message is very long (~1 K) and has been shortened to a maximum of 1000 characters for viewing in this context.
Please refer to the corresponding ASCII report for the full message.
//Input buffer for JTAG in clock
IBUFG IBUFG_01
(
.O(clkJTAGBuf),
.I(io_jtag_tck)
);
###################################################################################################################################################
# LPDDR MT46H32M16XXXX-5 #
###################################################################################################################################################
#NET "calib_done" LOC = P15 | IOSTANDARD = LVCMOS33;
#NET "error" LOC = P16 | IOSTANDARD = LVCMOS33;
#NET "c3_sys_rst_n" LOC = L15 | IOSTANDARD = LVCMOS33 | PULLDOWN; # Pin 7 of Header P9
#NET "mcb3_dram_a[0]" LOC = J7 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[10]" LOC = F4 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[11]" LOC = D3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[12]" LOC = G6 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[1]" LOC = J6 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[2]" LOC = H5 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[3]" LOC = L7 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[4]" LOC = F3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[5]" LOC = H4 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[6]" LOC = H3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[7]" LOC = H6 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[8]" LOC = D2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_a[9]" LOC = D1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_ba[0]" LOC = F2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_ba[1]" LOC = F1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_cas_n" LOC = K5 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_ck" LOC = G3 | IOSTANDARD = DIFF_MOBILE_DDR;
#NET "mcb3_dram_ck_n" LOC = G1 | IOSTANDARD = DIFF_MOBILE_DDR;
#NET "mcb3_dram_cke" LOC = H7 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dm" LOC = K3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[0]" LOC = L2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[10]" LOC = N2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[11]" LOC = N1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[12]" LOC = T2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[13]" LOC = T1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[14]" LOC = U2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[15]" LOC = U1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[1]" LOC = L1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[2]" LOC = K2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[3]" LOC = K1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[4]" LOC = H2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[5]" LOC = H1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[6]" LOC = J3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[7]" LOC = J1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[8]" LOC = M3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dq[9]" LOC = M1 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dqs" LOC = L4 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_ras_n" LOC = L5 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_udm" LOC = K4 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_udqs" LOC = P2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_we_n" LOC = E3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_rzq" LOC = N4 | IOSTANDARD = MOBILE_DDR;
output [12:0] io_sdram_ADDR, Address inputs mcb3_dram_a[x]
output [1:0] io_sdram_BA, Bank address inputs (bank selection) mcb3_dram_ba[x]
inout [15:0] io_sdram_DATA, Data input/output mcb3_dram_dq[x]
output io_sdram_DQ_writeEnable, ?
output [1:0] io_sdram_DQM, Data mask: in my IC (dm,dqs,udm,udqs) ?
output io_sdram_CASn, Column address strobe mcb3_dram_cas_n
output io_sdram_CKE, Clock enable: mcb3_dram_cke
output io_sdram_CSn, Chip select: LOW active ?
output io_sdram_RASn, RAS - row addres strobe mcb3_dram_ras_n
output io_sdram_WEn, part of command mcb3_dram_we_n
#NET "mcb3_dram_dm" LOC = K3 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_dqs" LOC = L4 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_udm" LOC = K4 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_dram_udqs" LOC = P2 | IOSTANDARD = MOBILE_DDR;
#NET "mcb3_rzq" LOC = N4 | IOSTANDARD = MOBILE_DDR;
Briey uses IS42x320D SDRAM as an external memory. That controller has been developed in Spinal HDL and attached to the SoC. RISCV is an instruction set SPEC, isn't a SoC implementation. You have to do one of two things, either you develop the memory controller of your board and attach it to the Briey SoC, or simply use the on-chip ram.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?