BrieySOC Project Status (04/28/2019 - 11:26:16)
Project File: BrieySoC01.xise Parser Errors: No Errors
Module Name: BrieySOC Implementation State: Placed and Routed
Target Device: xc6slx9-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,222 11,440 28%  
    Number used as Flip Flops 3,222      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 4,067 5,720 71%  
    Number used as logic 3,419 5,720 59%  
        Number using O6 output only 2,559      
        Number using O5 output only 174      
        Number using O5 and O6 686      
        Number used as ROM 0      
    Number used as Memory 568 1,440 39%  
        Number used as Dual Port RAM 40      
            Number using O6 output only 12      
            Number using O5 output only 0      
            Number using O5 and O6 28      
        Number used as Single Port RAM 512      
            Number using O6 output only 512      
            Number using O5 output only 0      
            Number using O5 and O6 0      
        Number used as Shift Register 16      
            Number using O6 output only 11      
            Number using O5 output only 0      
            Number using O5 and O6 5      
    Number used exclusively as route-thrus 80      
        Number with same-slice register load 63      
        Number with same-slice carry load 17      
        Number with other load 0      
Number of occupied Slices 1,322 1,430 92%  
Number of MUXCYs used 652 2,860 22%  
Number of LUT Flip Flop pairs used 4,519      
    Number with an unused Flip Flop 1,589 4,519 35%  
    Number with an unused LUT 452 4,519 10%  
    Number of fully used LUT-FF pairs 2,478 4,519 54%  
    Number of unique control sets 156      
    Number of slice register sites lost
        to control set restrictions
441 11,440 3%  
Number of bonded IOBs 83 200 41%  
    Number of LOCed IOBs 70 83 84%  
    IOB Flip Flops 32      
Number of RAMB16BWERs 3 32 9%  
Number of RAMB8BWERs 8 64 12%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 5 16 31%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 16 200 8%  
    Number used as ILOGIC2s 16      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 16 200 8%  
    Number used as OLOGIC2s 16      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 4 16 25%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.24      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentniedz. 28. kwi 11:23:17 2019   
Translation ReportCurrentniedz. 28. kwi 11:23:26 2019001 Info (0 new)
Map ReportCurrentniedz. 28. kwi 11:25:02 2019015 Warnings (14 new)9 Infos (2 new)
Place and Route ReportCurrentniedz. 28. kwi 11:26:00 201909 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentniedz. 28. kwi 11:26:15 2019003 Infos (0 new)
Bitgen ReportOut of Datepon. 15. kwi 17:26:14 201908 Warnings (7 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Datepon. 15. kwi 17:26:14 2019
WebTalk Log FileOut of Datepon. 15. kwi 17:26:18 2019

Date Generated: 04/30/2019 - 13:29:01