both rising_edge(clk) and faling_edge(clk) in one progrm,ok?

[vvsvv]

rising_edge

may I use rising_edge(clk) in process A, and at the same time

using faling_edge(clk) in Process B???????

BOTH process A and process B in just one architecture!

MAY I ?

(spartan2 FPGA , in VHDL!)

THANKS!

 

[fant123]

rising_edge(clk)

Yes you can!

In VHDL every process is a concurrential statement, and your structure on rising edge wakeup processA e on falling edge wakeup Process B

The code is also synthesizable by Xilinx.

 

[vvsvv]

rising_edge clk

thank first.
however, I heard that only coolrunner series have the ablity that may synthesis both rising_edge(clk) and falling_edge(clk), right?

DO xilinx's FPGA have the same ablitiy ?

thanks.

 

[Vonn]

using rising_edge in a process

Yes you can use both clock edges with any fpga but take care that you will reduce your maximum allowed frequency to the half

 

[weilijun]

faling_edge vhdl

You can use both rising_edge and falling_edge in an architecture. All work can be left for synthesis tool to do.

 

[bibo1978]

rising_edge(clk) and

Of course you can but this is a bad design habit and your timing requirement will be hard to meet also the timing analysis will be hard to deduce, so unless there is no way except this then you have to do it.

You have to take care of setup and hold requirements for both registers and you can't simply pass data from a rising edge register to a falling edge register.

that's all folks

 

[alphi]

risingedge(clk)

you can realize it,you can program and use tool to simulate it well.

 

[Al Farouk]

vhdl code rising_edge and falling_edge

Yes you can, and using rising or falling edge using constraints highly depend on your design. I want to add two things
1- If you have uncertain in any issue simply try it and see what the synthesizer will result, also this experiment will help you to deeply understand what the members explain.

2- bibo1978 say that
"you can't simply pass data from a rising edge register to a falling edge register"

you can do so as long as the setup and hold time is meet.

 

[xworld2008]

Re: both rising_edge(clk) and faling_edge(clk) in one progrm

Do you use latch . if you use latch it will about "timing borrow"