booth multiplier design

[tabascorez]

Hello

May somebody please help me with this. I have the following code, and now I want to use it to implement a variable length multiplier. How can I expand this code in order to achieve this?

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
module booth_mul #(parameter WIDTH=4)
 (input clk,
  input enable,
  input [WIDTH-1:0]multiplier,                         
  input [WIDTH-1:0]multiplicand,
  output reg [2*WIDTH-1:0]product);
   
  parameter IDLE = 2'b00,
                ADD  = 2'b01,
                SHIFT   = 2'b10,
                OUTPUT = 2'b11;
reg  [1:0]  current_state, next_state; 
reg  [2*WIDTH+1:0] a_reg,s_reg,p_reg,sum_reg; 
reg  [WIDTH-1:0]      iter_cnt;
wire [WIDTH:0]         multiplier_neg; 
 always @(posedge clk)
     if (!enable) current_state = IDLE;
    else         current_state = next_state;
always @* begin
next_state = 2'bx;
case (current_state)
   IDLE:   if (enable)  next_state = ADD;
                else  next_state = IDLE;
   ADD:   next_state = SHIFT;
   SHIFT: if (iter_cnt==WIDTH) next_state = OUTPUT;
                else   next_state = ADD;
   OUTPUT:  next_state = IDLE;
endcase
end
assign multiplier_neg = -{multiplier[WIDTH-1],multiplier};
 
always @(posedge clk) begin
    case (current_state)
      IDLE :  begin
            a_reg    <= {multiplier[WIDTH-1],multiplier,{(WIDTH+1){1'b0}}};
            s_reg    <= {multiplier_neg,{(WIDTH+1){1'b0}}};
            p_reg    <= {{(WIDTH+1){1'b0}},multiplicand,1'b0};
            iter_cnt <= 0;
         end
            ADD  :  begin
           case (p_reg[1:0])
              2'b01       : sum_reg <= p_reg+a_reg;
              2'b10       : sum_reg <= p_reg+s_reg;
              2'b00,2'b11 : sum_reg <= p_reg ;
                  endcase
     
                  iter_cnt <= iter_cnt + 1;
 
           end
           SHIFT :  begin
        p_reg <= {sum_reg[2*WIDTH+1],sum_reg[2*WIDTH+1:1]};
           end
           OUTPUT: product =  p_reg>>1;
endcase
end
endmodule

---

 

[ads-ee]

What do you mean by "multiplier length"? Did you mean to say the width of the operands?

If you meant the width of the operands then just change the WIDTH=4 value to something that matches your operand widths.

Regards

 

[tabascorez]

I mean depending on the number of operands, it should dynamically be able to perform multiplication from 8bit operands to 64 bit operands (8,16,24,...)
The code should now be modified for that.

 

[ads-ee]

I mean depending on the number of operands, it should dynamically be able to perform multiplication from 8bit operands to 64 bit operands (8,16,24,...)
The code should now be modified for that.

First you're saying number of operands then you state the bit widths....which one do you want to parameterize?

As I already stated in post #2. The parameter WIDTH can change the width of the input operands multiplier and multiplicand to 8-bits, 16-bits, 24-bits, 32-bits, etc. The code you originally posted has operands that default to 4-bits.

Regards.

 

[tabascorez]

If I write it to multiply like say 2 48 bit numbers, will it still work fine when I use it to multiply 2 16 bit numbers?
Because if I understand what you want to say, you just mean to change the number of bits to the maximum bit width yh?

 

[ads-ee]

If I write it to multiply like say 2 48 bit numbers, will it still work fine when I use it to multiply 2 16 bit numbers?
Because if I understand what you want to say, you just mean to change the number of bits to the maximum bit width yh?

So what you really want is to allow variable width inputs? That wasn't at all clear from your first post.

Just set the WDITH parameter to maximum and add logic outside the module to reformat the input data so you get the correct results. Like if it's 2's complement sign extend to the WIDTH-bits for the inputs.