rahdirs
Advanced Member level 1
Hi,
I generally work with VHDL,but in my present design i need to instantiate a VHDL module in verilog.
In verilog,i'm at beginner level
So,part of VHDL module goes like this:
In verilog,i see that there is no boolean type, so how can i instantiate this ?
Will something like this work ?
I generally work with VHDL,but in my present design i need to instantiate a VHDL module in verilog.
In verilog,i'm at beginner level
So,part of VHDL module goes like this:
Code:
entity adc08d1500 is
generic(
TIMING_CHECK : boolean := false;
DEBUG : boolean := true;
-- and so on
)
In verilog,i see that there is no boolean type, so how can i instantiate this ?
Will something like this work ?
Code:
adc08d1500 #
(.TIMING_CHECK ("\false"),
.DEBUG ("\true"),
//
)
u_adc08d1500 (
);