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Boolean parameter in verilog

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rahdirs

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Hi,

I generally work with VHDL,but in my present design i need to instantiate a VHDL module in verilog.
In verilog,i'm at beginner level

So,part of VHDL module goes like this:

Code:
entity adc08d1500 is
generic(
  TIMING_CHECK      : boolean  := false;
    DEBUG             : boolean := true;
 -- and so on

)

In verilog,i see that there is no boolean type, so how can i instantiate this ?
Will something like this work ?

Code:
adc08d1500 #
(.TIMING_CHECK            ("\false"),
  .DEBUG                       ("\true"),
//
) 
u_adc08d1500 (

);
 

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You should write a quick testcase...like this:

Code Verilog - [expand]
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module tc;
 
  // pass a boolean to VHDL from Verilog
  bool #(
    .BOOL1  (1),
    .BOOL2  (0)
  ) UUT ();
 
endmodule



Code VHDL - [expand]
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entity BOOL is
generic (
  BOOL1 : boolean := false;
  BOOL2 : boolean := true
);
end entity;
 
 
architecture behave of BOOL is
begin
  process
  begin
    if (BOOL1 = false) then
      report "BOOL1 is false";
    else
      report "BOOL1 is true";
    end if;
    if (BOOL2 = true) then
      report "BOOL2 is true";
    else
      report "BOOL2 is false";
    end if;
    wait for 100ns;
  end process;
end architecture;



You'll note that you use 1 for true and 0 for false, I believe anything other than 0 (within reason or 32-bits!) will be considered a true in VHDL when passed from Verilog. You could always use a verilog define for the true and false.


Code Verilog - [expand]
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// using a define
`define true 1
`define false 0
 
.BOOL1 (`true),
.BOOL2 (`false)
 
// or using a localparam/parameter
localparam true = 1;
localparam false = 0;
 
.BOOL1 (true),
.BOOL2 (false)

 

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