I agree, that synthesis in Verilog and VHDL is similar in many regards. However, the problem mainly addressed by the cummings paper, unpredictable behaviour and simulation to synthesis mismatch related to blocking statements can't happen in VHDL, because it's equivalent to blocking statements, variable assignments, have only process local visibility.
The cummings paper is discussing, why these problem are brought up in Verilog coding, if the well-known rules are ignored. But in my opinion, there is no general problem of evaluation order besides this special point.