alam.tauqueer
Full Member level 2
vhdl blocking assignment
Hi,
Can any one tell me what is the difference between the below mention code ,and what would be the issues if we are using blocking statment in sequencial logic
//////////////////////////////////////
always@(posedge clk)
begin
if(reset)
begin
q1 = 0;
q2 = 0;
end
else
begin
q1 = d1;
q2 = d2;
end
end
/////////////////////////////////
always@(posedge clk)
begin
if(reset)
begin
q1 <= 0;
q2 <= 0;
end
else
begin
q1 <= d1;
q2 <= d2;
end
end
///////////////////////////////////
Hi,
Can any one tell me what is the difference between the below mention code ,and what would be the issues if we are using blocking statment in sequencial logic
//////////////////////////////////////
always@(posedge clk)
begin
if(reset)
begin
q1 = 0;
q2 = 0;
end
else
begin
q1 = d1;
q2 = d2;
end
end
/////////////////////////////////
always@(posedge clk)
begin
if(reset)
begin
q1 <= 0;
q2 <= 0;
end
else
begin
q1 <= d1;
q2 <= d2;
end
end
///////////////////////////////////