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Blocking and Non-Blocking assignment

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alam.tauqueer

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vhdl blocking assignment

Hi,

Can any one tell me what is the difference between the below mention code ,and what would be the issues if we are using blocking statment in sequencial logic

//////////////////////////////////////
always@(posedge clk)
begin
if(reset)
begin
q1 = 0;
q2 = 0;
end
else
begin
q1 = d1;
q2 = d2;
end
end
/////////////////////////////////
always@(posedge clk)
begin
if(reset)
begin
q1 <= 0;
q2 <= 0;
end
else
begin
q1 <= d1;
q2 <= d2;
end
end
///////////////////////////////////
 

FvM

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blocking assignments vhdl

Hello,

1. there is no difference in this case,
2. behaviour would be different, if a assigned register value is used in another assignment effective on posedge clk
3. I don't see a particular issue, apart from function not behaving as intended. Both assignment techniques could be meaningful.

An an implication of blocking assignment, logic function could depend on statement order, cause you can have mutiple assignments to a register in a sequence, each taking effect immediately. With non-blocking assignment, function is independant of statement order, cause any assignment takes effect in the next clock cycle.

Regards,
Frank
 

NanhTrang

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blocking and non-blocking assignments

Hi,
Correct me if I'm wrong.
There's some guideline that we should follow:
1. When modeling sequential logic, use nonblocking assignments.
2. When modeling combinational logic with an always block, use blocking assignments.
These can help you avoid all the mismatch between simulation and synthesis.
 

FvM

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blocking assignment vhdl

Hello,

I'm not sure in which situation you get "mismatch between simulation and synthesis". I think, a mismatch between programmers intention and the function actually coded is the more common case. You should know what you are doing.

Your differentiation between sequential logic and combinational always blocks generally leads in the right direction. However, when describing synthesisable logic, the term "sequential" should be better replaced or supplemented by the term "synchronous", which characterizes the functional quality. Any assignment in the context of an "synchronous" always clock (posedge, negedge) instantiates a clock synchronous flipflop, which effectively operates non-blocking.

If you use blocking statements in this context, this could have different meanings. As in your original example, it could have no particular meaning and then would be inadequate, possibly misleading. Or it could instantiate additional combinational logic executing before non-blocking assignments. In VHDL, you have to use a separate VARIABLE object instead of a SIGNAL (= reg) to achieve this functionality.

In a combinational always block, non-blocking assignments don't have a reasonable purpose to my opinion.

As a detailed Verilog description, I prefer the Synopsys HDL compiler reference manual (identical in parts with the Xilinx Foundation Express verilog reference) http://www.stanford.edu/class/ee108b/labs/verilog_reference.pdf

Regards,
Frank
 

alam.tauqueer

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blocking assignments

Hi Frank,

I am fully agree with you but I was confuse like if we are using a blocking assignment in case of sequential always block as the example given above than how it is different from a non-blocking assignment.

I have one more question here is there any simulation synthesis mismatch in case of blocking assignment?
And what would be the harware ? It will be same hardware which we ll get through non-blocking assignment?
 

santumevce1412

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verilog mixing blocking non-blocking

For designing the sequential circuits, we define using non blocking statements because all the events r to be changed at the edge of the clock and for designing combinational circuits, we use blocking statements, as clk event is not a criteria..
 

FvM

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blocking non blocking mix

Hello,

thank you for linking the SNUG paper. It is really instructive and probably answers most questions raised in this discussion, also regarding possible mismatches between synthesis and simulation. It effectively could end the discussion.

I have a minor differences regarding the mixed cases (Guideline #5) in synchronous always blocks, which can be meaningful in some cases to my opinion. But I share the authors viewpoint, that alternative constructs better avoid misunderstandings. In so far I also agree Guideline #5, others anyway.

Regards,
Frank
 

vamsi_addagada

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vhdl mixing blocking and non-blocking assignments

hi ajay
the systhesis out put is first code got one FF that is connect the d1,d2,
second code getting the o/p is the 2FF

vamsi
 

alam.tauqueer

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blocking and non blocking assignment vhdl

Ok so in the above code we will not see any difference between blocking and non-blocking assignment.

Can any one please tell me where would be difference come into picture if we will use blocking assignment in case of sequential circuit.

It wil help us to get a better understanding.

Tauqueer
 

FvM

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snug-verilog blocking,non-blocking

Read the snug paper linked by NanhTrang. Would be a wast of time trying to explain the topic better.
 

NanhTrang

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verilog blocking vs non blocking assignment

Hi,
@Frank: Maybe I'm not good enough to code mix blocking and non-blocking assignments so I just simply separate them.
@Tauqueer: Please take a look at the paper I posted above. It have everything you are asking for.
 

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non blocking assignment on same clock

Hello,

Maybe I'm not good enough to code mix blocking and non-blocking assignments so I just simply separate them.
I think that's basically o.k. My view is formed by VHDL, which I use mostly. As I said, you have an VARIABLE object there, that receives "blocking assignments" (the "blocking" term isn't used in VHDL, only a ":=" operator instead of "<="). One possible purpose is to assign intermediate results to a VARIABLE object, possibly chaining multiple assignments to the same variable in a sequence. The final result can be assigned to a SIGNAL (= reg) within the same clock cycle. In a similar Verilog construct, you would mix blocking and non-blocking assignments.

Regards,
Frank
 

alam.tauqueer

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blocking non blocking assignments vhdl

I went through the paper now things are clear to me .

Thanks alot to all.

Regards
Tauqueer
 

madhavisai

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snug paper, blocking and non blocking

if u use non blocking assignment statements the values are assigned after current simulation,whereas in blocking values r assingned straight away
one more thing in posedge of clock if u write blocking in synthesis u will get ff/latch
 

mohaddin

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xilinx blocking vs non blocking

Hi Alll

Just go through verilog Basics by salman palnitkar,
its good book for verilog basics.

regards
Mohi
 

basha_vlsi

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blocking and non-blocking in vhdl

Both statement blocks are correct.

But using non blocing stmt assignment is good practice and using blocking stmt is bad coding style
 

Tan

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blocking non-blocking assignment

correct me if i am wrong..

Blocking assignment is similar to the variable assignment in vhdl...
and non-blocking is similar to signal assignment in vhdl..

In blocking the data is assigned immediately but in non -blocking the data is assigend in the next clock cycle..

please let me know if i am wrong..
 

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