blocking assignment vhdl
Hello,
I'm not sure in which situation you get "mismatch between simulation and synthesis". I think, a mismatch between programmers intention and the function actually coded is the more common case. You should know what you are doing.
Your differentiation between sequential logic and combinational always blocks generally leads in the right direction. However, when describing synthesisable logic, the term "sequential" should be better replaced or supplemented by the term "synchronous", which characterizes the functional quality. Any assignment in the context of an "synchronous" always clock (posedge, negedge) instantiates a clock synchronous flipflop, which effectively operates non-blocking.
If you use blocking statements in this context, this could have different meanings. As in your original example, it could have no particular meaning and then would be inadequate, possibly misleading. Or it could instantiate additional combinational logic executing before non-blocking assignments. In VHDL, you have to use a separate VARIABLE object instead of a SIGNAL (= reg) to achieve this functionality.
In a combinational always block, non-blocking assignments don't have a reasonable purpose to my opinion.
As a detailed Verilog description, I prefer the Synopsys HDL compiler reference manual (identical in parts with the Xilinx Foundation Express verilog reference)
Regards,
Frank