Blockage Cell in Placement -Soc Encounter

[dionieco]

Hi all,
i am trying do place and route of a digital project.
I loaded the file of configuration and do floorplanning.
After this i do placement.(Standard Cells).
The problem is: when i do the clock tree synthesize, load the Clock.ctstch, the cells change his position and overlap each other.
How i fixed the position of cells after placement??

Thank you!!

 

[shelby]

Normally you don't fix cells before CTS, but CTS should not be causing cells to overlap unless there is no where to put the cts buffers. What is your utilization? (do a checkPlace)

To fix overlap cells you can do refinePlace, but again you shouldn't need to do this

 

[dionieco]

Oh...Thank you...
yua are right.
I was using "utilization" taller and because this had overlap.
Of the fact, the error was the file .conf, where was set for 85 %.

 

[kumar_eee]

"refinePlace" will help you to remove the overlaps!.